公开(公告)号：US20180275736A1

公开(公告)日：2018-09-27

申请号：US15468527

申请日：2017-03-24

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Baruch SCHNARCH

IPC: G06F1/32 ,  H03L7/099 ,  G06F13/42

CPC classification number: G06F1/3203 ,  G06F13/42 ,  G06F2213/0012 ,  H03L7/0995

Abstract: Embodiments are generally directed to phase lock loop bypass for board level testing of systems. An embodiment of system includes a power management block for the system; multiple IO (input/output) blocks; a phase lock loop (PLL) block for each of the IO blocks, each of the phase lock loop blocks being switchable between providing an output of a PLL clock signal or providing a replacement clock signal as clocking for the respective IO block; and a read only memory for storage of firmware. In some embodiments, the firmware includes elements to enable operation of the plurality of IO blocks utilizing replacement clocking.