公开(公告)号：US11360876B2

公开(公告)日：2022-06-14

申请号：US16845512

申请日：2020-04-10

Applicant: Intel Corporation

Inventor： Michael Lemay ,  Beeman Strong

IPC: G06F11/34 ,  G06F11/30 ,  G06F21/57 ,  G06F21/56

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

公开(公告)号：US20230195593A1

公开(公告)日：2023-06-22

申请号：US17556751

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Claudia Romo ,  Jonathan Combs ,  Beeman Strong

IPC: G06F11/34 ,  G06F11/30 ,  G06F11/07

CPC classification number: G06F11/3466 ,  G06F11/3409 ,  G06F11/3072 ,  G06F11/076

Abstract: In one embodiment, an apparatus includes: at least one core to execute instructions; and a plurality of fixed counters coupled to the at least one core, the plurality of fixed counters to count events during execution on the at least one core, at least some of the plurality of fixed counters to count event information of a highest level of a hierarchical performance monitoring organization. Other embodiments are described and claimed.

公开(公告)号：US20230185695A1

公开(公告)日：2023-06-15

申请号：US17551774

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Markus Metzger ,  Beeman Strong

IPC: G06F11/36

CPC classification number: G06F11/3636

Abstract: An embodiment of an integrated circuit may comprise a processor and circuitry coupled to the processor to generate non-timing packets associated with a trace of an execution of code on the processor, generate timing packets associated with the trace of the execution of the code on the processor, wherein the timing packets include at least a full timestamp timing packet and a periodic timing packet, identify a low density section of the trace of the execution of the code on the processor, and suppress generation of periodic timing packets during the identified low density section of the trace of the execution of the code on the processor. Other embodiments are disclosed and claimed.

公开(公告)号：US11960375B2

公开(公告)日：2024-04-16

申请号：US17834211

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Michael Lemay ,  Beeman Strong

IPC: G06F11/34 ,  G06F11/30 ,  G06F21/56 ,  G06F21/57

CPC classification number: G06F11/3466 ,  G06F11/3024 ,  G06F21/56 ,  G06F21/577 ,  G06F2221/033

Abstract: Processor trace systems and methods are described. For example, one embodiment comprises executing instrumented code by a compiler, the instrumented code including at least one call to un-instrumented code. The compiler can determine the at least one call to un-instrumented code is a next call to be executed. A resume tracing instruction can be inserted into the instrumented code prior to the at least one call to the un-instrumented code. The resume tracing instruction can be executed to selectively add processor tracing to the at least one call to the un-instrumented code, and the at least one call to the un-instrumented code can be executed.

公开(公告)号：US20230315470A1

公开(公告)日：2023-10-05

申请号：US17708933

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Matthew Merten ,  Beeman Strong ,  Moshe Cohen ,  Ahmad Yasin ,  Andreas Kleen ,  Stanislav Bratanov ,  Karthik Gopalakrishnan ,  Angela Schmid ,  Grant Zhou

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F11/34

CPC classification number: G06F9/3814 ,  G06F9/30101 ,  G06F9/321 ,  G06F11/3409

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：US11016773B2

公开(公告)日：2021-05-25

申请号：US16585287

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Salmin Sultana ,  Beeman Strong ,  Ravi Sahita

IPC: G06F9/38 ,  G06F9/445 ,  G06F11/34 ,  G06F9/48 ,  G06F9/30

Abstract: Embodiments described herein provide for a computing device comprising a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.

公开(公告)号：US11614939B2

公开(公告)日：2023-03-28

申请号：US17359337

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US11061807B2

公开(公告)日：2021-07-13

申请号：US16235489

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Beeman Strong ,  Matthew C. Merten ,  Jason Agron

IPC: G06F11/00 ,  G06F11/36

Abstract: A method for tracing software code executing on a core of a processor is described. The method includes generating a set of packets for a trace packet stream based on a main cycle counter, which maintains a count of cycles elapsing in the core since a packet was emitted into the trace packet stream, and a commit cycle counter, which maintains a cycle count in the core since the last commit operation, wherein the generating comprises (1) storing a value of the main cycle counter in the commit cycle counter in response to detecting a commit operation and (2) storing a value of the commit cycle counter in the main cycle counter in response to detecting an abort in the core; and emitting the set of packets from the processor into the trace packet stream for tracing execution of the software code.

公开(公告)号：US20200026519A1

公开(公告)日：2020-01-23

申请号：US16585287

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Salmin Sultana ,  Beeman Strong ,  Ravi Sahita

IPC: G06F9/38 ,  G06F9/445 ,  G06F9/30 ,  G06F9/48 ,  G06F11/34

Abstract: Embodiments described herein provide for a computing device comprising a hardware processor including a processor trace module to generate trace data indicative of an order of instructions executed by the processor, wherein the processor trace module is configurable to selectively output a processor trace packet associated with execution of a selected non-deterministic control flow transfer instruction.

公开(公告)号：US10331452B2

公开(公告)日：2019-06-25

申请号：US14126313

申请日：2013-06-27

Applicant: Intel Corporation

Inventor： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

IPC: G06F9/30 ,  G06F11/36

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.