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    Compacted context state management
    2.
    发明授权
    Compacted context state management 有权

    公开(公告)号：US09898330B2

    公开(公告)日：2018-02-20

    申请号：US14076341

    申请日：2013-11-11

    Applicant: Intel Corporation

    Inventor： Atul Khare ,  Leena Puthiyedath ,  Asit Mallick ,  Jim Coke ,  Michael Mishaeli ,  Gilbert Neiger ,  Vivekananthan Sanjeepan ,  Jason Brandt

    IPC: G06F9/46 ,  G06F9/30

    CPC classification number: G06F9/461 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/30101

    Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

    DEVICE, SYSTEM AND METHOD FOR IDENTIFYING A SOURCE OF LATENCY IN PIPELINE CIRCUITRY
    3.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR IDENTIFYING A SOURCE OF LATENCY IN PIPELINE CIRCUITRY 审中-公开

    公开(公告)号：US20200233772A1

    公开(公告)日：2020-07-23

    申请号：US16748382

    申请日：2020-01-21

    Applicant: Intel Corporation

    Inventor： Jonathan Combs ,  Jason Brandt

    IPC: G06F11/34 ,  G06F11/30 ,  G06F9/54

    Abstract: Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

    USER-LEVEL INTERPROCESSOR INTERRUPTS
    7.
    发明申请
    USER-LEVEL INTERPROCESSOR INTERRUPTS 有权

    公开(公告)号：US20230099517A1

    公开(公告)日：2023-03-30

    申请号：US17561452

    申请日：2021-12-23

    Applicant: Intel Corporation

    Inventor： Gilbert Neiger ,  Asit Mallick ,  Rajesh Sankaran ,  Hisham Shafi ,  Vedvyas Shanbhogue ,  Vivekananthan Sanjeepan ,  Jason Brandt

    IPC: G06F9/48 ,  G06F9/54 ,  G06F9/30

    Abstract: Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.

    Apparatus and method to identify the source of an interrupt
    8.
    发明授权
    Apparatus and method to identify the source of an interrupt 有权

    公开(公告)号：US11614939B2

    公开(公告)日：2023-03-28

    申请号：US17359337

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

    IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

    Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

    SIMULATION STATE TO DETECT TRANSIENT EXECUTION ATTACK
    9.
    发明申请
    SIMULATION STATE TO DETECT TRANSIENT EXECUTION ATTACK 有权

    公开(公告)号：US20220198023A1

    公开(公告)日：2022-06-23

    申请号：US17130722

    申请日：2020-12-22

    Applicant: Intel Corporation

    Inventor： Ashwini Gopinath ,  Jason Brandt ,  Stephen Robinson

    IPC: G06F21/57 ,  G06F9/455

    Abstract: An embodiment of an apparatus includes memory to store a simulation model, a processor communicatively coupled to the memory, and logic communicatively coupled to the processor and the memory, the logic to run a simulation on the simulation model, identify one or more signals in the simulation model that contains data that should not be visible through any incidental channels, and selectively convert the identified one or more signals to an incidental-data state while the simulation runs. Other embodiments are disclosed and claimed.

    CONTEXT-BASED MEMORY INDIRECT BRANCH TARGET PREDICTION
    10.
    发明申请
    CONTEXT-BASED MEMORY INDIRECT BRANCH TARGET PREDICTION 有权

    公开(公告)号：US20220197661A1

    公开(公告)日：2022-06-23

    申请号：US17128814

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Ke Sun ,  Rodrigo Branco ,  Kekai Hu ,  Jason Brandt

    IPC: G06F9/38

    Abstract: An embodiment of an integrated circuit may comprise a branch target predictor to provide a branch target prediction for one or more instructions, the branch target predictor including circuitry to identify a memory indirect branch in the one or more instructions, and provide a predicted target of the memory indirect branch based on a context of the memory indirect branch. Other embodiments are disclosed and claimed.

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