公开(公告)号：US09542193B2

公开(公告)日：2017-01-10

申请号：US13730704

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Enrique De Lucas ,  Pedro Marcuello ,  Oren Ben-Kiki ,  Ilan Pardo ,  Yuval Yosef

IPC: G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3009 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867

Abstract: A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.

Abstract translation: 描述了一种具有负载碰撞检测电路的半导体芯片，该电路包括第一起爆滤波器电路。 半导体芯片具有存储冲突检测电路，该电路包括第二盛盛滤波器电路。 该半导体芯片具有能够执行与负载碰撞检测电路和存储冲突检测电路耦合的有序并行线程的一个或多个处理单元。 负载碰撞检测电路和存储碰撞检测电路是检测较年轻的存储器用于所述线程和较小负载的负载操作，用于所述线程的存储操作。

公开(公告)号：US20160328820A1

公开(公告)日：2016-11-10

申请号：US15212934

申请日：2016-07-18

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US10157063B2

公开(公告)日：2018-12-18

申请号：US13631402

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzelez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

公开(公告)号：US20160027144A1

公开(公告)日：2016-01-28

申请号：US14878336

申请日：2015-10-08

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/20 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US09922393B2

公开(公告)日：2018-03-20

申请号：US14878336

申请日：2015-10-08

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US09904977B2

公开(公告)日：2018-02-27

申请号：US15212934

申请日：2016-07-18

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US10101999B2

公开(公告)日：2018-10-16

申请号：US15403101

申请日：2017-01-10

Applicant: INTEL CORPORATION

Inventor： Enrique De Lucas ,  Pedro Marcuello ,  Oren Ben-Kiki ,  Ilan Pardo ,  Yuval Yosef

IPC: G06F9/30 ,  G06F9/38

Abstract: A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.

公开(公告)号：US20190004916A1

公开(公告)日：2019-01-03

申请号：US16026870

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC: G06F11/30 ,  G06F12/0862 ,  G06F11/34

Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

公开(公告)号：US09940686B2

公开(公告)日：2018-04-10

申请号：US14277239

申请日：2014-05-14

Applicant: Intel Corporation

Inventor： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/36 ,  G06T15/00 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

公开(公告)号：US09374542B2

公开(公告)日：2016-06-21

申请号：US14228684

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Kyriakos Stavrou ,  Pedro Marcuello ,  Grigorios Magklis ,  Javier Carretero Casado ,  Juan Fernandez ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou

IPC: H04N5/357 ,  H04N5/378 ,  H04N5/232

CPC classification number: H04N5/357 ,  H04N5/23229 ,  H04N5/378

Abstract: An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.

Abstract translation: 描述图像信号处理器。 图像信号处理器包括块检查电路。 块检查电路包括比较电路，用于将发光像素值的块与在发光像素值的块之后由图像信号处理器处理的各个发光像素值进行比较。 块检查电路还包括用于在各个发光像素值的块之一与发光像素值的块匹配的情况下将条目记录在表中的电路。 图像信号处理器用于存储发光像素值块的图像信号处理结果，并且将存储的结果作为各个发光像素值的块中的一个的相应结果存在，如果各个发光像素值的块之一 匹配像素值块。