公开(公告)号：US20230315473A1

公开(公告)日：2023-10-05

申请号：US17712139

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Muhammad Azeem ,  Rangeen Basu Roy Chowdhury ,  Xiang Zou ,  Malihe Ahmadi ,  Joju Joseph Zajo ,  Ariel Sabba ,  Ammon Christiansen ,  Polychronis Xekalakis ,  Eliyah Kilada

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/382 ,  G06F9/3873 ,  G06F9/30149

Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.

公开(公告)号：US10157063B2

公开(公告)日：2018-12-18

申请号：US13631402

申请日：2012-09-28

Applicant: INTEL CORPORATION

Inventor： Polychronis Xekalakis ,  Pedro Marcuello ,  Alejandro Vicente Martinez ,  Christos E. Kotselidis ,  Grigorios Magklis ,  Fernando Latorre ,  Raul Martinez ,  Josep M. Codina ,  Enric Gibert Codina ,  Crispin Gomez Requena ,  Antonio Gonzelez ,  Mirem Hyuseinova ,  Pedro Lopez ,  Marc Lupon ,  Carlos Madriles ,  Daniel Ortega ,  Demos Pavlou ,  Kyriakos A. Stavrou ,  Georgios Tournavitis

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

公开(公告)号：US09817642B2

公开(公告)日：2017-11-14

申请号：US14751052

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Jason M. Agron

IPC: G06F9/30 ,  G06F9/45 ,  G06F9/38 ,  G06F9/455 ,  G06F9/44

CPC classification number: G06F8/41 ,  G06F8/52 ,  G06F9/30054 ,  G06F9/30145 ,  G06F9/30174 ,  G06F9/30185 ,  G06F9/3806 ,  G06F9/4484 ,  G06F9/455 ,  G06F9/4552

Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

公开(公告)号：US09710389B2

公开(公告)日：2017-07-18

申请号：US14643354

申请日：2015-03-10

Applicant: INTEL CORPORATION

Inventor： Oleg Margulis ,  Sumit Ahuja ,  Polychronis Xekalakis ,  Yongjun Park ,  Vineeth Mekkat ,  Igor Yanover ,  Sebastian Winkel ,  Ethan Schuchman

IPC: G06F12/06 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F12/0875 ,  G06F9/38 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/467 ,  G06F2212/1008 ,  G06F2212/452

Abstract: A processor and method are described for alias detection. For example, one embodiment of an apparatus comprises: reordering logic to receive a set of read and write operations in a program order and to responsively reorder the read and write operations; adjustment information attachment logic to associate adjustment information with one or more of the set of read and write operations, wherein for a read operation the adjustment information is to indicate a number of write operations which the read operation has bypassed and for a write operation the adjustment information is to indicate a number of read operations which have bypassed the write operation; and out-of-order processing logic to determine whether execution of the reordered read and write operations will result in a conflict based, at least in part, on the adjustment information associated with the one or more reads and writes.

公开(公告)号：US20160179538A1

公开(公告)日：2016-06-23

申请号：US14576915

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： JAMISON D. COLLINS ,  Jayesh Iyer ,  Sebastian Winkel ,  Polychronis Xekalakis ,  Howard H. Chen ,  Rupert Brauch

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

Abstract translation: 用于使用堆栈同步指令来实现和维护谓词值堆栈的方法和装置的实施例。 在一个实施例中，该装置是一种无序的硬件/软件协同设计的处理器，其包括明确地管理谓词寄存器堆栈以便在执行的分支之间保持堆栈一致性的指令，其将可变数量的谓词值推送到谓词堆栈。 在一个实施例中，基于栈的谓词寄存器实现能够通过早期重命名谓词寄存器来实现早期分支计算和早期分支错误预测恢复。

公开(公告)号：US10795681B2

公开(公告)日：2020-10-06

申请号：US14580603

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Sumit Ahuja

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.

公开(公告)号：US20190004916A1

公开(公告)日：2019-01-03

申请号：US16026870

申请日：2018-07-03

Applicant: Intel Corporation

Inventor： Raul Martinez ,  Enric Gibert Codina ,  Pedro Lopez ,  Marti Torrents Lapuerta ,  Polychronis Xekalakis ,  Georgios Tournavitis ,  Kyriakos A. Stavrou ,  Demos Pavlou ,  Daniel Ortega ,  Alejandro Martinez Vicente ,  Pedro Marcuello ,  Grigorios Magklis ,  Josep M. Codina ,  Crispin Gomez Requena ,  Antonio Gonzalez ,  Mirem Hyuseinova ,  Christos Kotselidis ,  Fernando Latorre ,  Marc Lupon ,  Carlos Madriles

IPC: G06F11/30 ,  G06F12/0862 ,  G06F11/34

Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

公开(公告)号：US20220129763A1

公开(公告)日：2022-04-28

申请号：US17130661

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sumeet Bandishte ,  Jayesh Gaur ,  Polychronis Xekalakis ,  Ariel Sabba ,  Deborah Marr ,  Sreenivas Subramoney

IPC: G06N5/00 ,  G06N5/04

Abstract: An embodiment of an integrated circuit may comprise a front end unit, and circuitry coupled to the front end unit, the circuitry to provide a high confidence, multiple branch offset predictor. For example, the circuitry may be configured to identify an entry in a multiple-taken-branch prediction table that corresponds to a conditional branch instruction, determine if a confidence level of the entry exceeds a threshold confidence level, and, if so determined, provide multiple taken branch predictions that stem from the conditional branch instruction from the entry in the multiple-taken-branch prediction table. Other embodiments are disclosed and claimed.

公开(公告)号：US20210096866A1

公开(公告)日：2021-04-01

申请号：US17062556

申请日：2020-10-03

Applicant: Intel Corporation

Inventor： Polychronis Xekalakis ,  Sumit Ahuja

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.

公开(公告)号：US10409763B2

公开(公告)日：2019-09-10

申请号：US14319265

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Patrick P. Lai ,  Ethan Schuchman ,  David Keppel ,  Denis M. Khartikov ,  Polychronis Xekalakis ,  Joshua B. Fryman ,  Allan D. Knies ,  Naveen Neelakantam ,  Gregor Stellpflug ,  John H. Kelm ,  Mirem Hyuseinova Seidahmedova ,  Demos Pavlou ,  Jaroslaw Topp

IPC: G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/455

Abstract: Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.