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公开(公告)号：US20180329867A1
公开(公告)日：2018-11-15
申请号：US15948179
申请日：2018-04-09
Applicant: Intel Corporation
Inventor： Enric Herrero Abellanas , Marc Lupon , Ayose J. Falcon , Frederico C. Pratas , Fernando Latorre , Pedro Lopez
CPC classification number: G06F17/15 , G06F17/153 , G06K9/4609 , G06K9/627 , G06N3/04 , G06N3/0454 , G06N3/063
Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
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公开(公告)号：US10061587B2
公开(公告)日：2018-08-28
申请号：US14496113
申请日：2014-09-25
Applicant: Intel Corporation
Inventor： David Pardo Keppel , Denis M. Khartikov , Fernando LaTorre , Marc Lupon , Grigorios Magklis , Naveen Neelakantam , Georgios Tournavitis , Polychronis Xekalakis
CPC classification number: G06F9/30185 , G06F9/384 , G06F9/3857
Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.
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公开(公告)号：US20170220524A1
公开(公告)日：2017-08-03
申请号：US15454340
申请日：2017-03-09
Applicant: Intel Corporation
Inventor： Enric Herrero Abellanas , Marc Lupon , Ayose J. Falcon , Frederico C. Pratas , Fernando Latorre , Pedro Lopez
CPC classification number: G06F17/15 , G06F17/153 , G06K9/4609 , G06K9/627 , G06N3/04
Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
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4.发明授权公开(公告)号：US12032653B2
公开(公告)日：2024-07-09
申请号：US17306877
申请日：2021-05-03
Applicant: Intel Corporation
Inventor： Frederico C. Pratas , Ayose J. Falcon , Marc Lupon , Fernando Latorre , Pedro Lopez , Enric Herrero Abellanas , Georgios Tournavitis
IPC: G06F17/15 , G06F12/0875 , G06N3/04 , G06N3/063
CPC classification number: G06F17/153 , G06F12/0875 , G06N3/04 , G06N3/063 , G06F2212/1024
Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
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5.发明授权公开(公告)号：US10997273B2
公开(公告)日：2021-05-04
申请号：US15521856
申请日：2015-11-19
Applicant: Intel Corporation
Inventor： Frederico C. Pratas , Ayose J. Falcon , Marc Lupon , Fernando Latorre , Pedro Lopez , Enric Herrero Abellanas , Georgios Tournavitis
IPC: G06F17/15 , G06N3/063 , G06F12/0862 , G06F12/0875 , G06N3/04
Abstract: An apparatus and method are described for distributed and cooperative computation in artificial neural networks. For example, one embodiment of an apparatus comprises: an input/output (I/O) interface; a plurality of processing units communicatively coupled to the I/O interface to receive data for input neurons and synaptic weights associated with each of the input neurons, each of the plurality of processing units to process at least a portion of the data for the input neurons and synaptic weights to generate partial results; and an interconnect communicatively coupling the plurality of processing units, each of the processing units to share the partial results with one or more other processing units over the interconnect, the other processing units using the partial results to generate additional partial results or final results. The processing units may share data including input neurons and weights over the shared input bus.
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Patent Agency Ranking
公开(公告)号：US09971540B2
公开(公告)日：2018-05-15
申请号：US14861701
申请日：2015-09-22
Applicant: INTEL CORPORATION
Inventor： Enric Herrero Abellanas , Georgios Tournavitis , Frederico C. Pratas , Marc Lupon , Fernando Latorre , Pedro Lopez , Ayose J. Falcon
CPC classification number: G06F3/0644 , G06F3/0604 , G06F3/0683 , G06F17/153 , G06N3/063 , G06T1/60
Abstract: A storage device and method are described for performing convolution operations. For example, one embodiment of an apparatus to perform convolution operations comprises a plurality of processing units to execute convolution operations on input data and partial results; a unified scratchpad memory comprising a plurality of memory banks communicatively coupled to the plurality of processing units through a plurality of read/write ports, each of the plurality of memory banks partitioned to store both the input data and partial results; a control unit to allocate the input data and partial results to the memory banks to ensure a minimum quality of service in accordance with the specified number of read/write ports and the specified convolution operation to be performed.
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7.发明授权公开(公告)号：US09389871B2
公开(公告)日：2016-07-12
申请号：US13840363
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Marc Lupon , Grigorios Magklis , Sridhar Samudrala , Raul Martinez , Kyriakos A. Stavrou , Enric Gibert Codina
CPC classification number: G06F9/3861 , G06F9/3001 , G06F9/3017 , G06F9/45508
Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.
Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。
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8.发明申请公开(公告)号：US20190004916A1
公开(公告)日：2019-01-03
申请号：US16026870
申请日：2018-07-03
Applicant: Intel Corporation
Inventor： Raul Martinez , Enric Gibert Codina , Pedro Lopez , Marti Torrents Lapuerta , Polychronis Xekalakis , Georgios Tournavitis , Kyriakos A. Stavrou , Demos Pavlou , Daniel Ortega , Alejandro Martinez Vicente , Pedro Marcuello , Grigorios Magklis , Josep M. Codina , Crispin Gomez Requena , Antonio Gonzalez , Mirem Hyuseinova , Christos Kotselidis , Fernando Latorre , Marc Lupon , Carlos Madriles
IPC: G06F11/30 , G06F12/0862 , G06F11/34
Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
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公开(公告)号：US09778909B2
公开(公告)日：2017-10-03
申请号：US15332721
申请日：2016-10-24
Applicant: Intel Corporation
Inventor： Sridhar Samudrala , Grigorios Magklis , Marc Lupon , David R. Ditzel
CPC classification number: G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
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公开(公告)号：US09613001B2
公开(公告)日：2017-04-04
申请号：US14136302
申请日：2013-12-20
Applicant: Intel Corporation
Inventor： Enric Herrero Abellanas , Marc Lupon , Ayose J. Falcon , Frederico C. Pratas , Fernando Latorre , Pedro Lopez
CPC classification number: G06F17/15 , G06F17/153 , G06K9/4609 , G06K9/627 , G06N3/04
Abstract: Systems and methods for performing convolution operations. An example processing system comprises: a processing core; and a convolver unit to apply a convolution filter to a plurality of input data elements represented by a two-dimensional array, the convolver unit comprising a plurality of multipliers coupled to two or more sets of latches, wherein each set of latches is to store a plurality of data elements of a respective one-dimensional section of the two-dimensional array.
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