公开(公告)号：US20210013145A1

公开(公告)日：2021-01-14

申请号：US16955760

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Florian GSTREIN ,  Cen TAN ,  Rami HOURANI

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.

公开(公告)号：US20200168462A1

公开(公告)日：2020-05-28

申请号：US16637177

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Cen TAN

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/306

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.