公开(公告)号：US11456248B2

公开(公告)日：2022-09-27

申请号：US16955760

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Florian Gstrein ,  Cen Tan ,  Rami Hourani

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.

公开(公告)号：US11217456B2

公开(公告)日：2022-01-04

申请号：US16955012

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： James M. Blackwell ,  Scott B. Clendenning ,  Cen Tan ,  Marie Krysak

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: Selective etching and controlled atomic layer etching of transition metal oxide films for device fabrication, and the resulting devices, are described. In an example, method of dry etching a film includes forming a transition metal oxide film having a latent pore-forming material therein. The method also includes removing a surface portion of the latent pore-forming material of the transition metal oxide film to form a porous region of the transition metal oxide film. The method also includes removing the porous region of the transition metal oxide film.

公开(公告)号：US11270887B2

公开(公告)日：2022-03-08

申请号：US16637177

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Patricio E. Romero ,  Scott B. Clendenning ,  Florian Gstrein ,  Cen Tan

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L29/51

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.