公开(公告)号：US09602160B2

公开(公告)日：2017-03-21

申请号：US14521961

申请日：2014-10-23

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Changhong Lin

IPC: H04B3/32 ,  H04J1/12 ,  H04J3/10 ,  G06F13/40 ,  H04L25/14

CPC classification number: H04B3/32 ,  G06F13/40 ,  H04J1/12 ,  H04J3/10 ,  H04L25/08 ,  H04L25/14

Abstract: Described is an apparatus which comprises: a first buffer to receive a first signal from a first transmission media; a second buffer to receive a second signal from a second transmission media separate from the first transmission media; a first summing node coupled to the first buffer, the first summing node to receive output of the first buffer; and a first digital adjustment circuit which is operable to drive a first adjustment signal to the first summing node when a transition edge of the second signal is detected.

公开(公告)号：US20240113743A1

公开(公告)日：2024-04-04

申请号：US17957053

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Harry Muljono ,  Changhong Lin ,  Mohammad Mamunur Rashid

IPC: H04B3/32

CPC classification number: H04B3/32

Abstract: An improved circuit for generating a crosstalk noise cancellation signal may be used for combining the crosstalk noise cancellation signal with a victim signal without a crosstalk cancelling capacitor. The improved crosstalk cancellation circuit may be used to provide improved TX crosstalk cancellation, and may be used to provide improved performance of increasingly higher speed memory systems regardless of memory process technology, enabling improvements to existing and future memory systems and other communication systems. The improved crosstalk cancellation circuit may include a transmission amplifier to receive a first digital signal and generate a first analog output signal, a crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal, and a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal.

公开(公告)号：US10528515B2

公开(公告)日：2020-01-07

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin Li ,  Changhong Lin ,  James A. McCall ,  Harry Muljono

IPC: G06F13/40 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  G06F13/16

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.