公开(公告)号：US20210408704A1

公开(公告)日：2021-12-30

申请号：US17470552

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  James McCall ,  Qin Li

IPC: H01R12/71 ,  H01R12/55 ,  H05K1/18 ,  H01R13/24

Abstract: Systems, apparatuses and methods may provide for a memory module that includes a dynamic random access memory (DRAM), a first plurality of contact pads positioned along a first side of the DRAM, a first plurality of L-shaped contacts, wherein each of the first plurality of L-shaped contacts is soldered to one of the first plurality of contact pads, a second plurality of contact pads positioned along a second side of the DRAM, and a second plurality of L-shaped contacts, wherein each of the second plurality of L-shaped contacts is soldered to one of the second plurality of contact pads.

公开(公告)号：US10467160B2

公开(公告)日：2019-11-05

申请号：US15719742

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Xiang Li ,  Yunhui Chu ,  Jun Liao ,  George Vergis ,  James A. McCall ,  Charles C. Phares ,  Konika Ganguly ,  Qin Li

IPC: G11C5/02 ,  G06F13/16 ,  G11C5/06 ,  G06F1/18 ,  H01R12/73 ,  G11C5/04 ,  G11C7/10

Abstract: A method is described. The method includes receiving DDR memory channel signals from a motherboard through a larger DIMM motherboard connector. The method includes routing the signals to one of first and second smaller form factor connectors. The method includes sending the DDR memory channel signals to a DIMM that is connected to the one of the first and second smaller form factor connectors.

公开(公告)号：US20170133083A1

公开(公告)日：2017-05-11

申请号：US14935291

申请日：2015-11-06

Applicant: Intel Corporation

Inventor： Qin Li ,  Min Wang

IPC: G11C11/4093

CPC classification number: G11C11/4093 ,  G06F13/4234 ,  G11C5/04 ,  H05K1/0243 ,  H05K2201/10159 ,  Y02D10/14 ,  Y02D10/151

Abstract: High capacity, high bandwidth memory devices and systems having on-board memory buffering are disclosed and described.

公开(公告)号：US10528515B2

公开(公告)日：2020-01-07

申请号：US15634991

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Qin Li ,  Changhong Lin ,  James A. McCall ,  Harry Muljono

IPC: G06F13/40 ,  G11C7/12 ,  G11C7/22 ,  H04B3/23 ,  G06F13/16

Abstract: An apparatus is described that includes a memory channel driver circuit having first driver circuitry to drive a data signal on a memory channel and second driver circuitry to drive an echo cancellation signal on the memory channel. The echo cancellation signal includes echo cancellation pulses that follow corresponding pulses of the data signal by an amount of time that causes the echo cancellation pulses to reduce reflections of the corresponding pulses of the data signal at a memory device that is coupled to the memory channel.