公开(公告)号：US20240088069A1

公开(公告)日：2024-03-14

申请号：US18260810

申请日：2021-02-26

Applicant: Intel Corporation

Inventor： Wenzhi Wang ,  Xiaoning Ye ,  Yunhui Chu ,  Chunfei Ye ,  James A. McCall

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L25/18 ,  H10B80/00 ,  H01L2223/6627

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.

公开(公告)号：US11335395B2

公开(公告)日：2022-05-17

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  Christopher P. Mozak ,  James A. McCall ,  Akshith Vasanth ,  Bill Nale

IPC: G11C11/4072 ,  G11C11/4096 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/406

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US11056179B2

公开(公告)日：2021-07-06

申请号：US16737666

申请日：2020-01-08

Applicant: Intel Corporation

Inventor： Chong J. Zhao ,  James A. McCall ,  Shigeki Tomishima ,  George Vergis ,  Kuljit S. Bains

IPC: G11C29/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/408 ,  H01L27/108

Abstract: Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.

公开(公告)号：US10965047B2

公开(公告)日：2021-03-30

申请号：US16431498

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Jong-Ru Guo ,  Yunhui Chu ,  Jun Liao ,  Kai Xiao ,  Jingbo Li ,  Yuanhong Zhao ,  Mo Liu ,  Beomtaek Lee ,  James A. McCall ,  Jaejin Lee ,  Xiaoning Ye ,  Zuoguo Wu ,  Xiang Li

IPC: H05K7/00 ,  H01R12/71 ,  H01R13/66 ,  H01R103/00

Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.

公开(公告)号：US10943640B2

公开(公告)日：2021-03-09

申请号：US16177284

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis ,  James A. McCall ,  Ge Chang

IPC: G06F12/00 ,  G11C11/4074 ,  G06F3/06 ,  G11C7/10 ,  G11C8/06 ,  G06F13/16 ,  G11C11/408

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series.

公开(公告)号：US10541018B2

公开(公告)日：2020-01-21

申请号：US15716485

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： James A. McCall ,  Christopher P. Mozak ,  Christopher E. Cox ,  Yan Fu ,  Robert J. Friar ,  Hsien-Pao Yang

IPC: G11C11/40 ,  G11C11/4072 ,  G06F3/06

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

公开(公告)号：US10031868B2

公开(公告)日：2018-07-24

申请号：US15608846

申请日：2017-05-30

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall ,  Bryan K. Casper

IPC: G06F13/20 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F11/10

CPC classification number: G06F13/1657 ,  G06F11/10 ,  G06F13/4004 ,  G06F13/4022 ,  G06F13/4072 ,  G06F13/4217 ,  G06F13/4221 ,  G06F13/4234 ,  H04L25/4915 ,  Y02D10/14 ,  Y02D10/151

Abstract: Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

公开(公告)号：US09552164B2

公开(公告)日：2017-01-24

申请号：US14440066

申请日：2013-11-22

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G11C5/14 ,  G11C29/02

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收到的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器件。

公开(公告)号：US09218575B2

公开(公告)日：2015-12-22

申请号：US14018217

申请日：2013-09-04

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  James A. McCall

IPC: G06F3/00 ,  G06F13/00 ,  G06N99/00 ,  G05B13/02

CPC classification number: G06N99/005 ,  G05B13/02 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2207/2254

Abstract: I/O parameters are adjusted based on a number of errors detected in a received training signal. A controller device sends the training signal while a memory device is in a training mode. The memory device samples the training signal and the system causes an adjustment to at least one I/O parameter based on a detected number of errors. Either the controller or the memory device can perform the error detection, depending on the configuration of the system. Either an I/O parameter of the controller or an I/O parameter of the memory device can be adjusted, depending on the configuration of the system.

Abstract translation: 基于在接收到的训练信号中检测到的错误的数量来调整I / O参数。 控制器设备在存储设备处于训练模式时发送训练信号。 存储器件采样训练信号，并且系统基于检测到的错误数量对至少一个I / O参数进行调整。 控制器或存储设备可以根据系统的配置执行错误检测。 根据系统的配置，可以调整控制器的I / O参数或存储设备的I / O参数。

公开(公告)号：US09024665B2

公开(公告)日：2015-05-05

申请号：US13801759

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Derek M. Conrow ,  Aaron Martin ,  James A. McCall

IPC: H03K3/00 ,  H04B1/04

CPC classification number: H04B1/0475 ,  H03K19/018521 ,  H03K19/018585 ,  H03K19/018592 ,  H04L25/0278

Abstract: Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.

Abstract translation: 描述了一种集成电路（IC），其包括：用于耦合到传输线的输入 - 输出（I / O）焊盘; 耦合到I / O焊盘的电压模式驱动器，具有上拉驱动器和下拉驱动器的电压模式驱动器; 以及耦合到所述I / O焊盘的电流模式驱动器，所述电流模式驱动器可操作以与所述电压模式驱动器并联起作用。