公开(公告)号：US20190034365A1

公开(公告)日：2019-01-31

申请号：US15829524

申请日：2017-12-01

Applicant: Intel Corporation

Inventor： John V. LOVELACE ,  Christina JUE

IPC: G06F13/16 ,  G06F11/10 ,  G06F9/30

Abstract: Techniques for training a command/address (C/A) bus, including training internal command/address (C/A) signal lines of a memory module are described. In one example, a method of training a C/A bus involves a memory controller transmitting a first command to a DRAM with parity checking enabled, the first command to include valid parity and chip select asserted. The memory controller transmits commands in cycles before and after the first command to at least one DRAM with parity checking disabled, the commands to include invalid parity and chip select asserted. In response to detecting a parity error, the memory controller modifies a timing parameter to adjust timing for the internal C/A signal lines of the memory module.

公开(公告)号：US20220148639A1

公开(公告)日：2022-05-12

申请号：US17441667

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Tonia G. MORRIS ,  Christina JUE ,  Daniel BECERRA PEREZ ,  David G. ELLIS

IPC: G11C11/4076 ,  G11C11/4096

Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.