公开(公告)号：US20220148639A1

公开(公告)日：2022-05-12

申请号：US17441667

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Tonia G. MORRIS ,  Christina JUE ,  Daniel BECERRA PEREZ ,  David G. ELLIS

IPC: G11C11/4076 ,  G11C11/4096

Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

公开(公告)号：US20240385754A1

公开(公告)日：2024-11-21

申请号：US18570674

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Daocheng BU ,  Dujian WU ,  Yufu LI ,  Vincent ZIMMER

IPC: G06F3/06

Abstract: Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.

公开(公告)号：US20230041115A1

公开(公告)日：2023-02-09

申请号：US17794856

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Ping WU ,  Yingwen CHEN ,  Lei ZHU ,  Zhenglong WU ,  Tao XU

IPC: G06F9/4401 ,  G06F9/50

Abstract: Systems, apparatuses and methods may provide for technology that initializes an integrated memory of a processor during a boot sequence and conducts a runtime initialization of an external system memory associated with the processor. The technology may also bypass the runtime initialization of the external system memory during the boot sequence.