Flexible and scalable accelerator architecture

    公开(公告)号:US10713196B1

    公开(公告)日:2020-07-14

    申请号:US16227875

    申请日:2018-12-20

    申请人: INTEL CORPORATION

    摘要: The present disclosure is directed to accelerator circuitry useful in a network applications, such as cloud-based radio access networks. The accelerator circuitry includes interface circuitry that couples the accelerator circuitry to each of a plurality of processor circuits and to system memory circuitry. The accelerator circuitry also includes queue management circuitry, local storage circuitry, direct memory access (DMA) circuitry, and a plurality of accelerator circuits. In operation, the processor circuit communicates a message to the queue management circuitry. The message includes pointer data and prioritized data. The queue management circuitry enqueues the message in one of a plurality of queues. The DMA circuitry receives the message and locates a descriptor at the address designed by the pointer. The DMA circuitry retrieves input data, selects an accelerator circuit, and provides the input data to the selected accelerator circuit. The accelerator circuit returns output data to the DMA circuitry, The output data is stored in system memory circuitry.

    High speed turbo decoder
    2.
    发明授权

    公开(公告)号:US10084486B1

    公开(公告)日:2018-09-25

    申请号:US15720905

    申请日:2017-09-29

    申请人: Intel Corporation

    摘要: A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.