公开(公告)号：US20200167221A1

公开(公告)日：2020-05-28

申请号：US16203578

申请日：2018-11-28

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  BRYAN WHITE ,  ANKUR SHAH ,  MURALI RAMADOSS ,  DAVE PUFFER ,  ALTUG KOKER ,  ADITYA NAVALE ,  MAHESH NATU

IPC: G06F11/07 ,  G06T15/00

Abstract: Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.