公开(公告)号：US20170154012A1

公开(公告)日：2017-06-01

申请号：US15431527

申请日：2017-02-13

Applicant: Intel Corporation

Inventor： VARGHESE GEORGE ,  SANJEEV S. JAHAGIRDAR ,  DEBORAH T. MARR

IPC: G06F15/80 ,  G06F1/32 ,  G06F13/40

CPC classification number: G06F15/80 ,  G06F1/3206 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F13/4022 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/22

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

公开(公告)号：US20190073336A1

公开(公告)日：2019-03-07

申请号：US16103798

申请日：2018-08-14

Applicant: INTEL CORPORATION

Inventor： VARGHESE GEORGE ,  SANJEEV S. JAHAGIRDAR ,  DEBORAH T. MARR

IPC: G06F15/80 ,  G06F1/32 ,  G06F9/50 ,  G06F13/40

CPC classification number: G06F15/80 ,  G06F1/3206 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F13/4022 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/22

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.