公开(公告)号：US20200285294A1

公开(公告)日：2020-09-10

申请号：US16880167

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC: G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20170293332A1

公开(公告)日：2017-10-12

申请号：US15093042

申请日：2016-04-07

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  TOD F. SCHIFF ,  DORON RAJWAN ,  JEFFREY M. JULL ,  JAMES G. HERMERDING, II ,  NIR ROSENZWEIG ,  MAYTAL TOLEDANO ,  ALEXANDER B. UAN-ZO-LI

IPC: G06F1/26 ,  G08B21/18

Abstract: One embodiment provides an apparatus. The apparatus includes power control logic and a critical comparator. The power control logic is to determine a critical threshold (TC) based, at least in part, on an available input power value (Pin). The critical comparator is to compare a system power consumption value (Psys) and the critical threshold and to assert a processor critical throttle signal to a processor if the system power consumption value is greater than or equal to the critical threshold.

公开(公告)号：US20230063955A1

公开(公告)日：2023-03-02

申请号：US18048593

申请日：2022-10-21

Applicant: Intel Corporation

Inventor： DORON RAJWAN ,  EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  AVINASH N. ANANTHAKRISHNAN ,  DORIT SHAPIRA

IPC: G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.