公开(公告)号：US10198394B2

公开(公告)日：2019-02-05

申请号：US15283310

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US11163717B2

公开(公告)日：2021-11-02

申请号：US16921498

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20210056067A1

公开(公告)日：2021-02-25

申请号：US16921498

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20170344512A1

公开(公告)日：2017-11-30

申请号：US15283310

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC: G06F13/42 ,  G06F13/40 ,  H04L29/08

CPC classification number: G06F13/4282 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4068 ,  H04L67/1095 ,  H04L69/08

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.