公开(公告)号：US11749368B2

公开(公告)日：2023-09-05

申请号：US16729085

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Dana How

IPC: G11C29/12 ,  G11C29/56 ,  G11C29/00 ,  G11C29/14 ,  G06F15/78

CPC classification number: G11C29/12015 ,  G06F15/7807 ,  G11C29/14 ,  G11C29/56008 ,  G11C29/789 ,  G11C2029/1206

Abstract: An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.