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公开(公告)号：US20170025171A1
公开(公告)日：2017-01-26
申请号：US15195787
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Daniel J. Chu
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C7/1009 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2207/2263
Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
Abstract translation: 公开了将数据写入相变存储器阵列的技术。 在一个示例中，方法可以包括识别用于屏蔽相变存储器阵列中的单元并且将掩模逻辑路由到单元的掩模逻辑。 该方法还可以包括将输入数据路由到小区。 可以基于掩模逻辑选择性地防止或禁止针对单元的设置和复位脉冲。
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公开(公告)号：US20180068720A1
公开(公告)日：2018-03-08
申请号：US15690148
申请日：2017-08-29
Applicant: Intel Corporation
Inventor： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/0033 , G11C13/0064 , G11C13/0069
Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
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公开(公告)号：US10037799B2
公开(公告)日：2018-07-31
申请号：US15195787
申请日：2016-06-28
Applicant: Intel Corporation
Inventor： Daniel J. Chu
CPC classification number: G11C13/0004 , G11C7/1009 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2207/2263
Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
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Patent Agency Ranking
公开(公告)号：US09406378B2
公开(公告)日：2016-08-02
申请号：US14560410
申请日：2014-12-04
Applicant: Intel Corporation
Inventor： Daniel J. Chu
CPC classification number: G11C13/0004 , G11C7/1009 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2207/2263
Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
Abstract translation: 公开了将数据写入相变存储器阵列的技术。 在一个示例中，方法可以包括识别用于屏蔽相变存储器阵列中的单元并且将掩模逻辑路由到单元的掩模逻辑。 该方法还可以包括将输入数据路由到小区。 可以基于掩模逻辑选择性地防止或禁止针对单元的设置和复位脉冲。
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公开(公告)号：US10325652B2
公开(公告)日：2019-06-18
申请号：US15690148
申请日：2017-08-29
Applicant: Intel Corporation
Inventor： Daniel J. Chu , Raymond W. Zeng , Doyle Rivers
IPC: G11C13/00
Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.
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公开(公告)号：US09286975B2
公开(公告)日：2016-03-15
申请号：US14204376
申请日：2014-03-11
Applicant: Intel Corporation
Inventor： Daniel J. Chu , Kiran Pangal , Nathan R. Franklin , Prashant S. Damle , Hu Chaohong
CPC classification number: G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0035 , G11C13/0061 , G11C2013/0047 , G11C2013/0052
Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.
Abstract translation: 本公开涉及减轻交叉点存储器中的读取干扰。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控制器。 存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。
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公开(公告)号：US20150085570A1
公开(公告)日：2015-03-26
申请号：US14560410
申请日：2014-12-04
Applicant: Intel Corporation
Inventor： Daniel J. Chu
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C7/1009 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2207/2263
Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
Abstract translation: 公开了将数据写入相变存储器阵列的技术。 在一个示例中，方法可以包括识别用于屏蔽相变存储器阵列中的单元并且将掩模逻辑路由到单元的掩模逻辑。 该方法还可以包括将输入数据路由到小区。 可以基于掩模逻辑选择性地防止或禁止针对单元的设置和复位脉冲。
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公开(公告)号：US08913425B2
公开(公告)日：2014-12-16
申请号：US13796462
申请日：2013-03-12
Applicant: Intel Corporation
Inventor： Daniel J. Chu
CPC classification number: G11C13/0004 , G11C7/1009 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/0076 , G11C2207/2263
Abstract: Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.
Abstract translation: 公开了将数据写入相变存储器阵列的技术。 在一个示例中，方法可以包括识别用于屏蔽相变存储器阵列中的单元并且将掩模逻辑路由到单元的掩模逻辑。 该方法还可以包括将输入数据路由到小区。 可以基于掩模逻辑选择性地防止或禁止针对单元的设置和复位脉冲。
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