公开(公告)号：US10516439B2

公开(公告)日：2019-12-24

申请号：US15666436

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenein ,  James M. Shehadi

IPC: H04B3/487 ,  G06F11/00 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/3183 ,  G06F7/58

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

公开(公告)号：US09722663B2

公开(公告)日：2017-08-01

申请号：US14229460

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenein ,  James M. Shehadi

IPC: H04B3/46 ,  H04B3/487 ,  G06F11/00 ,  G01R31/3185 ,  G01R31/28

CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

公开(公告)号：US20170359099A1

公开(公告)日：2017-12-14

申请号：US15666436

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenein ,  James M. Shehadi

IPC: H04B3/487 ,  G06F11/00 ,  G01R31/28 ,  G01R31/3185

CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/318385 ,  G01R31/31855 ,  G06F7/58 ,  G06F11/00

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

公开(公告)号：US20150280781A1

公开(公告)日：2015-10-01

申请号：US14229460

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenien ,  James M. Shehadi

IPC: H04B3/46

CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

Abstract translation: 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。