公开(公告)号：US20240385754A1

公开(公告)日：2024-11-21

申请号：US18570674

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Zhenglong WU ,  Daocheng BU ,  Dujian WU ,  Yufu LI ,  Vincent ZIMMER

IPC: G06F3/06

Abstract: Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.

公开(公告)号：US20220093197A1

公开(公告)日：2022-03-24

申请号：US17421483

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Dujian WU ,  Shijian GE ,  Daocheng BU

IPC: G11C29/10 ,  G11C29/12 ,  G11C29/46 ,  G11C29/38

Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.