公开(公告)号：US20230195388A1

公开(公告)日：2023-06-22

申请号：US17555174

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： William Butera ,  David Webb ,  Mitchell Diamond ,  Steven Hsu ,  Amit Agarwal

IPC: G06F3/06 ,  G06F9/38

CPC classification number: G06F3/0667 ,  G06F9/3818 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods and apparatus relating to register file virtualization techniques are described. In an embodiment, a register file includes a plurality of register file cells. Each of the register file cells includes a register file entry and a shadow buffer. Logic circuitry causes storage of input data to the shadow buffer, while data stored in the register file entry is accessible to perform one or more operations. Other embodiments are also disclosed and claimed.

公开(公告)号：US09740617B2

公开(公告)日：2017-08-22

申请号：US14581097

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Samantika Sury ,  Simon Steely, Jr. ,  William Hasenplaugh ,  Joel Emer ,  David Webb

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0817

CPC classification number: G06F12/0833 ,  G06F12/0822 ,  G06F2212/283 ,  Y02D10/13

Abstract: Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

公开(公告)号：US20160179674A1

公开(公告)日：2016-06-23

申请号：US14581097

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Samantika Sury ,  Simon Steely, JR. ,  William Hasenplaugh ,  Joel Emer ,  David Webb

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0822 ,  G06F2212/283 ,  Y02D10/13

Abstract: Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

Abstract translation: 描述了控制高速缓存行相干性的方法和装置。 硬件处理器可以包括具有高速缓存以存储高速缓存行的第一处理器核心，第二组处理器核心，每个处理器核心包括高速缓存以存储高速缓存行的副本，以及高速缓存一致性逻辑以在标签目录中聚合确认 响应于来自第一处理器核心的请求来修改第二组处理器核心中的每个处理器核心中的高速缓存行的副本，并且向第一处理器核心发送合并确认消息，来自第二组处理器核心中的每一个的消息。