公开(公告)号：US09716226B2

公开(公告)日：2017-07-25

申请号：US15366364

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

公开(公告)号：US09543515B2

公开(公告)日：2017-01-10

申请号：US14073927

申请日：2013-11-07

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

Abstract translation: 公开了具有降低的电极 - 硫族化物界面电阻的相变存储单元和制造相变存储单元的方法：在电极层和硫族化物层之间形成界面层，并在硫族化物之间提供降低的电阻 的相变存储层和电极层。 示例性实施例提供界面层包括碳化钨，碳化钼，硼化钨或硼化钼，或其组合。 在一个示例性实施例中，界面层包括约1nm至约10nm的厚度。

公开(公告)号：US20170084835A1

公开(公告)日：2017-03-23

申请号：US15366364

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.