公开(公告)号：US09543515B2

公开(公告)日：2017-01-10

申请号：US14073927

申请日：2013-11-07

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

Abstract translation: 公开了具有降低的电极 - 硫族化物界面电阻的相变存储单元和制造相变存储单元的方法：在电极层和硫族化物层之间形成界面层，并在硫族化物之间提供降低的电阻 的相变存储层和电极层。 示例性实施例提供界面层包括碳化钨，碳化钼，硼化钨或硼化钼，或其组合。 在一个示例性实施例中，界面层包括约1nm至约10nm的厚度。

公开(公告)号：US09379321B1

公开(公告)日：2016-06-28

申请号：US14664745

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： Kuo-Wei Chang ,  Paolo Fantini

IPC: H01L45/00 ,  H01L27/24 ,  C03C3/00 ,  C03C3/04 ,  C03C3/062 ,  C03C3/32

CPC classification number: H01L45/143 ,  C03C3/00 ,  C03C3/04 ,  C03C3/062 ,  C03C3/32 ,  C03C3/321 ,  H01L27/2409 ,  H01L45/00 ,  H01L45/04 ,  H01L45/06 ,  H01L45/14 ,  H01L45/141

Abstract: Embodiments of the present disclosure describe chalcogenide glass compositions and chalcogenide switch devices (CSD.) The compositions generally may include 3% to 15%, silicon, 8% to 16% germanium in, greater than 45% selenium, and 20% to 35% arsenic, by weight. The amount of silicon and germanium in a composition generally may include more than 10% by weight. CSDs may include various compositions of chalcogenide glass, and a plurality of them may be used in a memory device, such as die with a memory component, and may be used in various electronic components and systems. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施方案描述了硫族化物玻璃组合物和硫族化物开关装置（CSD。）组合物通常可以包括3％至15％的硅，8％至16％的锗，大于45％的硒和20％至35％ 砷，重量。 组合物中硅和锗的量通常可以包括大于10重量％。 CSD可以包括硫族化物玻璃的各种组合物，并且它们中的多个可以用于诸如具有存储器组件的管芯的存储器件中，并且可以用于各种电子部件和系统中。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170084835A1

公开(公告)日：2017-03-23

申请号：US15366364

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.

公开(公告)号：US09716226B2

公开(公告)日：2017-07-25

申请号：US15366364

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： F. Daniel Gealy ,  Andrea Gotti ,  Davide Colombo ,  Kuo-Wei Chang

IPC: H01L21/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm.