公开(公告)号：US10073138B2

公开(公告)日：2018-09-11

申请号：US14979301

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Suraj Sindia ,  Robert Kwasnick ,  Dhruv Singh

IPC: H04L9/00 ,  G01R31/317 ,  G01R31/3177 ,  H04L9/08 ,  H04L9/32

CPC classification number: G01R31/31703 ,  G01R31/3177 ,  H04L9/0866 ,  H04L9/0891 ,  H04L9/3278 ,  H04L2209/34

Abstract: An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.

公开(公告)号：US20180095802A1

公开(公告)日：2018-04-05

申请号：US15283006

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Gordon McFadden ,  Pradeepsunder Ganesh ,  Stephen Thomas Palermo ,  Travis J. White ,  Ashok Raj ,  Vivek Garg ,  Dhruv Singh

IPC: G06F9/50

CPC classification number: G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.