公开(公告)号：US20210116982A1

公开(公告)日：2021-04-22

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

公开(公告)号：US10073138B2

公开(公告)日：2018-09-11

申请号：US14979301

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Suraj Sindia ,  Robert Kwasnick ,  Dhruv Singh

IPC: H04L9/00 ,  G01R31/317 ,  G01R31/3177 ,  H04L9/08 ,  H04L9/32

CPC classification number: G01R31/31703 ,  G01R31/3177 ,  H04L9/0866 ,  H04L9/0891 ,  H04L9/3278 ,  H04L2209/34

Abstract: An apparatus is described that includes a plurality of circuits each designed to exhibit a unique signature code that is determined from manufacturing tolerances associated with a manufacturing process used to manufacture the circuits. The apparatus also includes error circuitry to determine an error has arisen based on a change in signature codes from the plurality of circuits.

公开(公告)号：US12130688B2

公开(公告)日：2024-10-29

申请号：US17133226

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rahul Khanna ,  Xin Kang ,  Ali Taha ,  James Tschanz ,  William Zand ,  Robert Kwasnick

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/50

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize a guard band of a hardware resource. An example apparatus includes at least one storage device, and at least one processor to execute instructions to identify a phase of a workload based on an output from a machine-learning model, the phase based on a utilization of one or more hardware resources, and based on the phase, control a guard band of a first hardware resource of the one or more hardware resources.

公开(公告)号：US11556352B2

公开(公告)日：2023-01-17

申请号：US16222986

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Jamel Tayeb ,  Robert Kwasnick ,  Johan Van De Groenendaal

IPC: G06F9/445 ,  G06F15/167

Abstract: Examples provided herein provide a manner of monitoring performance characteristics of a central processing unit or other instruction executing hardware device and adjusting settings of the central processing unit or other instruction executing hardware device. Performance characteristics can be gathered and stored in a secure memory or storage device. The performance characteristics can be transmitted to a control center using a provisioned network transceiver that does not rely on an operating system executed by the central processing unit or the hardware platform of the central processing unit. The control center can determine settings that are to be applied by the central processing unit or instruction executing hardware device and transmit the settings for use by the central processing unit or instruction executing hardware device.