公开(公告)号：US20250006740A1

公开(公告)日：2025-01-02

申请号：US18216325

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vivek VISHWAKARMA ,  Jessica PANELLA ,  Sean PURSEL ,  Dincer UNLUER ,  Shaun MILLS ,  Hongqian SUN ,  Charles H. WALLACE

IPC: H01L27/12 ,  H01L21/84

Abstract: Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.