公开(公告)号：US20220406778A1

公开(公告)日：2022-12-22

申请号：US17353263

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Mohammad HASAN ,  Reken PATEL ,  Sean PURSEL ,  Jake JAFFE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

公开(公告)号：US20250006787A1

公开(公告)日：2025-01-02

申请号：US18215748

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Shao Ming KOH ,  Sean PURSEL ,  Charles H. WALLACE ,  Hongqian SUN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.

公开(公告)号：US20250098230A1

公开(公告)日：2025-03-20

申请号：US18370725

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Sean PURSEL ,  Dimitri KIOUSSIS ,  Lukas BAUMGARTEL ,  Mahdi AHMADI ,  Cortnie S. VOGELSBERG ,  Mengcheng LU ,  Omar Kyle HITE ,  Justin E. MUELLER ,  Lily Mao

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit structures having dual stress gates are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires, and a second vertical stack of nanowires laterally spaced apart from the first vertical stack of horizontal nanowires. An NMOS gate electrode is over the first vertical stack of horizontal nanowires, the NMOS gate electrode having a tensile layer extending from a top to a bottom of the first vertical stack of horizontal nanowires. A PMOS gate electrode is over the second vertical stack of horizontal nanowires, the PMOS gate electrode having a compressive layer extending from a top to a bottom of the second vertical stack of horizontal nanowires. The tensile layer of the NMOS gate electrode is not included in the PMOS gate electrode.

公开(公告)号：US20240395886A1

公开(公告)日：2024-11-28

申请号：US18202678

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Charles H. WALLACE ,  Shengsi LIU ,  Sean PURSEL

IPC: H01L29/423 ,  H01L23/522 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having partial channel cap removal, and methods of fabricating integrated circuit structures having partial channel cap removal, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires. A dielectric channel cap has an opening over the stack of nanowires. A gate electrode is over and around the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires. A conductive tap is on the gate electrode and in the opening in the dielectric channel cap. A dielectric layer is on the gate electrode and laterally adjacent to the conductive tap.

公开(公告)号：US20250006740A1

公开(公告)日：2025-01-02

申请号：US18216325

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vivek VISHWAKARMA ,  Jessica PANELLA ,  Sean PURSEL ,  Dincer UNLUER ,  Shaun MILLS ,  Hongqian SUN ,  Charles H. WALLACE

IPC: H01L27/12 ,  H01L21/84

Abstract: Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.

公开(公告)号：US20220399336A1

公开(公告)日：2022-12-15

申请号：US17347979

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Tsuan-Chung CHANG ,  Sean PURSEL

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

公开(公告)号：US20240105804A1

公开(公告)日：2024-03-28

申请号：US17954194

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sean PURSEL ,  Dan S. LAVRIC ,  Allen B. GARDINER ,  Jonathan HINKE ,  Wonil CHUNG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78696 ,  H01L21/823431

Abstract: Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.

公开(公告)号：US20240105801A1

公开(公告)日：2024-03-28

申请号：US17951974

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sukru YEMENICIOGLU ,  Raghuram GANDIKOTA ,  Krishna GANESAN ,  Sean PURSEL

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/775 ,  H01L2029/42388

Abstract: Integrated circuit structures having gate volume reduction, and methods of fabricating integrated circuit structures having gate volume reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first side and a second side. A dielectric backbone structure is along the first side of the stack of nanowires. The dielectric backbone structure has a bottom above a bottom of the sub-fin. A gate electrode is over the stack of nanowires and is along the second side of the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires.

公开(公告)号：US20240105771A1

公开(公告)日：2024-03-28

申请号：US17955485

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Sean PURSEL ,  Tsuan-Chung CHANG ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L27/0886 ,  H01L29/7851

Abstract: Integrated circuit structures having channel cap reduction, and methods of fabricating integrated circuit structures having channel cap reduction, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires, the stack of nanowires having a first end and a second end. A dielectric cap has a first portion vertically over the first end of the stack of nanowires and has a second portion vertically over the second end of the stack of nanowires. The dielectric cap is not vertically over a location between the first end and the second end of the stack of nanowires. A gate electrode is over and around the stack of nanowires and laterally between the first and second portions of the dielectric cap. A gate dielectric structure is between the gate electrode and the stack of nanowires.

公开(公告)号：US20220399445A1

公开(公告)日：2022-12-15

申请号：US17347034

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Tahir GHANI ,  Charles H. WALLACE ,  Conor P. PULS ,  Walid M. HAFEZ ,  Sairam SUBRAMANIAN ,  Justin S. SANDFORD ,  Saurabh MORARKA ,  Sean PURSEL ,  Mohammad HASAN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.