公开(公告)号：US20250006740A1

公开(公告)日：2025-01-02

申请号：US18216325

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Vivek VISHWAKARMA ,  Jessica PANELLA ,  Sean PURSEL ,  Dincer UNLUER ,  Shaun MILLS ,  Hongqian SUN ,  Charles H. WALLACE

IPC: H01L27/12 ,  H01L21/84

Abstract: Integrated circuit structures having backside source or drain contact differentiated access are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over a first conductive material having a first depth below the first epitaxial source or drain structure. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure over a second conductive material having a second depth below the second epitaxial source or drain structure, the second depth greater than the first depth.

公开(公告)号：US20240113109A1

公开(公告)日：2024-04-04

申请号：US17958291

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Robert JOACHIM ,  Shengsi LIU ,  Hongqian SUN ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/00

CPC classification number: H01L27/088 ,  H01L21/8234 ,  H01L23/564

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. In embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. The cap may include a metal. A top of the cap may be even with, or substantially even with, the top of the two gates. The plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. Other embodiments may be described and/or claimed.

公开(公告)号：US20250006787A1

公开(公告)日：2025-01-02

申请号：US18215748

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Shao Ming KOH ,  Sean PURSEL ,  Charles H. WALLACE ,  Hongqian SUN

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit structure includes a first vertical stack of horizontal nanowires or a first fin having a first lateral width. A first gate electrode is over the first vertical stack of horizontal nanowires or the first fin, the first gate electrode having a second lateral width. A second vertical stack of horizontal nanowires or a second fin is laterally spaced apart from the first vertical stack of horizontal nanowires or the second fin, the second vertical stack of horizontal nanowires or the second fin having a third lateral width, the third lateral width less than the first lateral width. A second gate electrode is over the second vertical stack of horizontal nanowires or the second fin, the second gate electrode laterally spaced apart from the first gate electrode, and the second gate electrode having a fourth lateral width, the fourth lateral width less than the second lateral width.

公开(公告)号：US20240113108A1

公开(公告)日：2024-04-04

申请号：US17958285

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sukru YEMENICIOGLU ,  Leonard P. GULER ,  Hongqian SUN ,  Shengsi LIU ,  Tahir GHANI ,  Baofu ZHU

IPC: H01L27/088 ,  H01L21/764 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/764 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.