利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.018 秒)

    Integrated circuits with machine learning extensions
    2.
    发明授权
    Integrated circuits with machine learning extensions 有权

    公开(公告)号：US11726744B2

    公开(公告)日：2023-08-15

    申请号：US17214526

    申请日：2021-03-26

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Kevin Hurd

    IPC分类号： G06F7/487 ,  G06F7/544

    CPC分类号： G06F7/4876 ,  G06F7/5443 ,  G06F2207/382 ,  G06F2207/3824

    摘要： An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

    FPGA Specialist Processing Block for Machine Learning
    3.
    发明申请
    FPGA Specialist Processing Block for Machine Learning 有权

    公开(公告)号：US20210182023A1

    公开(公告)日：2021-06-17

    申请号：US16914107

    申请日：2020-06-26

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

    IPC分类号： G06F7/523 ,  G06F7/50 ,  G06N20/00 ,  H03M7/24 ,  H03K19/17748

    摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

    Integrated circuits with machine learning extensions
    5.
    发明授权
    Integrated circuits with machine learning extensions 有权

    公开(公告)号：US12056461B2

    公开(公告)日：2024-08-06

    申请号：US17484845

    申请日：2021-09-24

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen

    IPC分类号： G06F7/544 ,  G06F7/485

    CPC分类号： G06F7/5443 ,  G06F7/485 ,  G06F2207/382 ,  G06F2207/3824

    摘要： An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS
    6.
    发明公开
    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS 审中-公开

    公开(公告)号：US20230342111A1

    公开(公告)日：2023-10-26

    申请号：US18216797

    申请日：2023-06-30

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Kevin Hurd

    IPC分类号： G06F7/487 ,  G06F7/544

    CPC分类号： G06F7/4876 ,  G06F7/5443 ,  G06F2207/3824 ,  G06F2207/382

    摘要： An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS
    7.
    发明申请
    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS 有权

    公开(公告)号：US20220012015A1

    公开(公告)日：2022-01-13

    申请号：US17484845

    申请日：2021-09-24

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Kevin Hurd

    IPC分类号： G06F7/544 ,  G06F7/485 ,  G06F7/483

    摘要： An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS
    9.
    发明申请
    INTEGRATED CIRCUITS WITH MACHINE LEARNING EXTENSIONS 有权

    公开(公告)号：US20210240440A1

    公开(公告)日：2021-08-05

    申请号：US17214526

    申请日：2021-03-26

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Kevin Hurd

    IPC分类号： G06F7/487 ,  G06F9/30 ,  G06F7/544

    摘要： An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

    Integrated circuits with machine learning extensions
    10.
    发明授权
    Integrated circuits with machine learning extensions 有权

    公开(公告)号：US10970042B2

    公开(公告)日：2021-04-06

    申请号：US16144904

    申请日：2018-09-27

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Kevin Hurd

    IPC分类号： G06F7/487 ,  G06F9/30 ,  G06F7/544

    摘要： An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.