公开(公告)号：US11520584B2

公开(公告)日：2022-12-06

申请号：US16914098

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/34 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US11907719B2

公开(公告)日：2024-02-20

申请号：US16914009

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/34 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

CPC classification number: G06F9/30101 ,  G06F7/50 ,  G06F7/523 ,  G06F7/556 ,  G06F9/30105 ,  G06F30/34 ,  G06F30/343 ,  G06F30/38 ,  G06N20/00 ,  H03K19/177 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US20210182023A1

公开(公告)日：2021-06-17

申请号：US16914107

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F7/523 ,  G06F7/50 ,  G06N20/00 ,  H03M7/24 ,  H03K19/17748

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US20210182022A1

公开(公告)日：2021-06-17

申请号：US16914098

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F7/523 ,  G06F7/556 ,  G06F7/50 ,  G06N20/00 ,  H03M7/24 ,  H03K19/177

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US20240176619A1

公开(公告)日：2024-05-30

申请号：US18435993

申请日：2024-02-07

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F9/30 ,  G06F7/483 ,  G06F7/50 ,  G06F7/523 ,  G06F7/556 ,  G06F30/34 ,  G06F30/343 ,  G06F30/38 ,  G06N20/00 ,  H03K19/177 ,  H03K19/17748 ,  H03M7/24

CPC classification number: G06F9/30101 ,  G06F7/50 ,  G06F7/523 ,  G06F7/556 ,  G06F9/30105 ,  G06F30/34 ,  G06F30/343 ,  G06F30/38 ,  G06N20/00 ,  H03K19/177 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

公开(公告)号：US11494186B2

公开(公告)日：2022-11-08

申请号：US16914107

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

IPC: G06F30/34 ,  G06F9/30 ,  G06N20/00 ,  G06F30/343 ,  G06F30/38 ,  G06F7/50 ,  G06F7/523 ,  H03K19/17748 ,  H03M7/24 ,  G06F7/556 ,  H03K19/177 ,  G06F7/483

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.