公开(公告)号：US10855305B2

公开(公告)日：2020-12-01

申请号：US16375572

申请日：2019-04-04

Applicant: Intel Corporation

Inventor： Roee Eitan ,  Ahmad B. Khairi ,  Yosi Sanhedrai ,  Ram Livne ,  Ilya Kraimer ,  Hen Sallem ,  Idan Lotan ,  Ariel Cohen ,  Dror Lazar

IPC: H03M1/38 ,  G06F13/40 ,  G06F13/16 ,  H03K5/24 ,  H03M1/12 ,  H03M1/46 ,  H03M1/08

Abstract: A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.

公开(公告)号：US10944411B1

公开(公告)日：2021-03-09

申请号：US16728601

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Mark Elzinga ,  Youngmin Park ,  Michael Bichan ,  Michael W. Altmann ,  Noam Familia ,  Vadim Levin ,  Dror Lazar

IPC: H03L7/10 ,  H03M3/00 ,  H03L7/099 ,  H03L7/18 ,  H03L7/187

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a first capacitor array, and a second capacitor array. The first circuitry may have an oscillator. The first capacitor array may have a set of first capacitors to tune the oscillator. The second capacitor array may have a second capacitor to tune the oscillator. A capacitance of the second capacitor may be greater than an average capacitance of the first capacitors. The second circuitry may be operable to synchronously activate the second capacitor and deactivate a number N of the first capacitors, and to synchronously deactivate the second capacitor and activate the N first capacitors, based on a predetermined sequence.

公开(公告)号：US12066959B2

公开(公告)日：2024-08-20

申请号：US17743297

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Vijayalakshmi Ramachandran ,  Mingming Xu ,  Dror Lazar

IPC: G06F13/20 ,  G01R31/28 ,  G05F1/46

CPC classification number: G06F13/20 ,  G01R31/2889 ,  G05F1/46 ,  G06F2213/40

Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.

公开(公告)号：US08711018B2

公开(公告)日：2014-04-29

申请号：US13781039

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Ehud Shoor ,  Dror Lazar ,  Assaf Benhamou

IPC: H03M9/00

CPC classification number: H03M9/00 ,  H04J3/0608

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括解串器，用于以第一速率接收串行数据，并响应于从反馈回路接收到的相位控制信号，输出对应于与帧对准边界对准的串行数据的并行数据帧 耦合在解串器和耦合到解串器的输出的接收器逻辑之间。 描述和要求保护其他实施例。

公开(公告)号：US20230367725A1

公开(公告)日：2023-11-16

申请号：US17743297

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Vijayalakshmi Ramachandran ,  Mingming Xu ,  Dror Lazar

IPC: G06F13/20 ,  G05F1/46 ,  G01R31/28

CPC classification number: G06F13/20 ,  G01R31/2889 ,  G05F1/46 ,  G06F2213/40

Abstract: Techniques and mechanisms for determining a reference voltage which is to be provided with an integrated circuit (IC) die. In an embodiment, the IC die comprises a resistor, and a hardware interface which accommodates coupling of the IC die to a test unit. The test unit provides functionality to perform an evaluation of a resistance of the resistor, wherein said resistance is indicative of the respective resistances of one or more other resistors of the IC die. Based on the evaluation, the test unit provides to the IC die an indication of a scale factor, wherein the reference voltage is generated based on the scale factor. In another embodiment, the IC die further comprises an amplifier circuit which receives the reference voltage, wherein a variable resistance circuit of the IC die is configured based on an output of the amplifier circuit.

公开(公告)号：US09973356B1

公开(公告)日：2018-05-15

申请号：US15475690

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ram Livne ,  Ro'ee Eitan ,  Yoel Krupnik ,  Vladislav Tsirkin ,  Tomer Fael ,  Dror Lazar ,  Ariel Cohen ,  Alexander Pogrebinsky ,  Adee Ofir Ran

IPC: H03L7/08 ,  H04L25/03 ,  H03G3/20 ,  H04L25/06

CPC classification number: H04L25/03057

Abstract: One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

公开(公告)号：US09568530B2

公开(公告)日：2017-02-14

申请号：US14527560

申请日：2014-10-29

Applicant: INTEL CORPORATION

Inventor： Ehud Udi Shoor ,  Dror Lazar ,  Adee O. Ran

IPC: G01R31/02 ,  G01M11/00 ,  H04B3/46 ,  H04B3/36

CPC classification number: G01R31/021 ,  G01M11/33 ,  H04B3/36 ,  H04B3/46

Abstract: Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable. The arrangement may further include a plurality of testing cables to concatenate two or more of the lanes of the active cable, to enable the transmission of the test pattern over the concatenated lanes of the active cable. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于测试多通道有源电缆的测试布置的配置。 在一个实施例中，测试装置可以包括测试模块，该测试模块包括与具有多个通道的有源电缆耦合的模式发生器，以产生将通过有源电缆传输的测试模式，其中测试模式将以 串联的有源电缆的至少两个或更多个通道，以及与有源电缆耦合以处理测试图案在有源电缆上传输的结果的处理单元。 该布置还可以包括多个测试电缆，以连接有源电缆的两条或更多条通道，以使测试图案能够在有源电缆的级联通道上传输。 可以描述和/或要求保护其他实施例。