公开(公告)号：US20180005944A1

公开(公告)日：2018-01-04

申请号：US15201388

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huet Goh ,  Jiun Hann Sir ,  Min Suet Lim ,  Khang Choong Yong

IPC: H01L23/535 ,  H01L21/48 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/535 ,  H01L21/4803 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5381 ,  H01L23/5383 ,  H01L2224/16225

Abstract: Electrical interconnect technology for a package substrate is disclosed. A substrate can include a first conductive element at least partially disposed in a first routing layer, and a second conductive element at least partially disposed in a second routing layer. The first and second routing layers are adjacent routing layers. The substrate can also include a third conductive element having first and second portions disposed in the first routing layer, and an intermediate third portion disposed in a “sub-interconnect layer” between the first and second routing layers.