公开(公告)号：US12096553B2

公开(公告)日：2024-09-17

申请号：US16572652

申请日：2019-09-17

Applicant: CARNEGIE MELLON UNIVERSITY

Inventor： Gary K. Fedder ,  Carmel Majidi ,  Philip R. LeDuc ,  Lee E. Weiss ,  Christopher J. Bettinger ,  Naser Naserifar

IPC: H05K1/02 ,  B29C33/40 ,  H01L21/48 ,  H05K1/18 ,  H05K3/30 ,  H05K3/38 ,  H05K3/46 ,  B05D3/10 ,  H01L23/31 ,  H05K5/06

CPC classification number: H05K1/0283 ,  B29C33/40 ,  H01L21/4803 ,  H05K1/02 ,  H05K1/185 ,  H05K3/30 ,  H05K3/38 ,  H05K3/4644 ,  A61B2562/125 ,  A61B2562/164 ,  B05D3/10 ,  B05D3/107 ,  B05D3/108 ,  H01L23/3121 ,  H05K5/065 ,  H05K2201/1003

Abstract: A flexible and stretchable integrated electronic device includes a substrate having a stiffness gradient, wherein a rigid electronic device is embedded within the substrate. The stiffness gradient within the substrate prevents delamination at the interface between the substrate and the embedded device. The stiffness gradient is accomplished by providing at least two distinct zones in the substrate with uniform stiffness, with each zone decreasing in stiffness as in a distance from the embedded device increases, or the gradient is accomplished by having a zone with a varying stiffness.

公开(公告)号：US20240274580A1

公开(公告)日：2024-08-15

申请号：US18433911

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L21/4803 ,  H01L23/42 ,  H01L24/32 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/32225 ,  H01L2225/06562 ,  H01L2225/06575

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate. The semiconductor device assembly includes a first semiconductor die above the substrate including an edge and a second semiconductor die in a stacked arrangement above the first semiconductor die. The second semiconductor die comprises an overhang portion extending beyond the edge. The semiconductor device assembly includes a terraced support structure between the overhang portion and the substrate. The terraced support structure may mitigate deflection of the overhang portion during a molding operation to prevent damage to the semiconductor device assembly.

公开(公告)号：US20240203856A1

公开(公告)日：2024-06-20

申请号：US18587998

申请日：2024-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： SHUO-MAO CHEN ,  FENG-CHENG HSU ,  SHIN-PUU JENG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49894 ,  H01L25/18 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/73204

Abstract: A method includes: forming a first interposer die, wherein the first interposer die comprises a first substrate and a first redistribution layer (RDL) over the first substrate; bonding the first interposer die to a second RDL; encapsulating the second RDL and the first interposer die with a first encapsulating layer; thinning the first interpose die to expose the first RDL; and bonding a first semiconductor die to the first RDL.

公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US20240194561A1

公开(公告)日：2024-06-13

申请号：US18554309

申请日：2021-05-12

Applicant: Nippon Telegraph and Telephone Corporation

Inventor： Yuta Shiratori

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/78 ,  H01L29/205 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L23/373 ,  H01L21/4803 ,  H01L21/7806 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/7371

Abstract: A hetero-junction bipolar transistor includes a heat dissipation structure made of metal, having one end in contact with top of a heat dissipation substrate around an element part and formed to penetrate a protective layer, and includes a collector wiring formed on the protective layer in contact with top of the heat dissipation structure and a collector electrode, a base contact electrode connected to the base electrode and penetrating the protective layer, and a base wiring connected to the base contact electrode and formed on the protective layer.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.

公开(公告)号：US11942408B2

公开(公告)日：2024-03-26

申请号：US17749218

申请日：2022-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/18 ,  H01L23/14 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/49811 ,  H01L23/49894 ,  H01L25/18 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/73204

Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.

公开(公告)号：US20240096720A1

公开(公告)日：2024-03-21

申请号：US18512939

申请日：2023-11-17

Applicant: LX SEMICON CO., LTD.

Inventor： Deog Soo KIM ,  Tae Ryong KIM

IPC: H01L23/24 ,  H01L21/48 ,  H01L23/00 ,  H01L23/373 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/24 ,  H01L21/4803 ,  H01L23/3735 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06505 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2924/0132 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

Abstract: A semiconductor module having a double-sided heat dissipation structure according to one aspect of the present invention, which can secure the gap between the first and second heat dissipation substrates without using existing spacers, includes a first heat dissipation substrate and a second heat dissipation substrate arranged to face each other; a guide stack disposed between the first heat dissipation substrate and the second heat dissipation substrate, and having an opening area for mounting a semiconductor die in a pattern; and a semiconductor die mounted within the opening area.

公开(公告)号：US11830780B2

公开(公告)日：2023-11-28

申请号：US17135907

申请日：2020-12-28

Applicant: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD. ,  FOXCONN INTERCONNECT TECHNOLOGY LIMITED

Inventor： Shan-Yong Cheng

IPC: H01R12/70 ,  H01R12/71 ,  H01R13/514 ,  H01L23/053 ,  H01L21/48 ,  H01L23/40

CPC classification number: H01L23/053 ,  H01L21/4803 ,  H01L23/4093 ,  H01R12/7017 ,  H01R12/716 ,  H01R13/514

Abstract: An electrical connector is essentially composed of a pair of half housings opposite to each other in a longitudinal direction to commonly form a receiving cavity for receiving a CPU. Each half housing is equipped with a plurality of contacts with corresponding contacting sections upwardly extending into the receiving cavity for mating with the CPU. A single pick-up cap includes a plate with a plurality of claws adapted to be engaged within locking recesses in exterior sides of the half housings, a plurality of positioning blocks adapted to extend into the receiving cavity so as to cooperate with the claws to sandwich the periphery wall of the housing therebetween in the longitudinal direction for securing the half housings to the pick-up cap. Therefore, both the pair of half housings may be grasped by the single pick-up cap for mounting and soldering to PCB at the same time.

公开(公告)号：US20230369370A1

公开(公告)日：2023-11-16

申请号：US17743463

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Jung Chen ,  Tsung-Fu Tsai ,  Szu-Wei Lu ,  Wei-An Tsao ,  Che-Yuan Yang ,  Chien-Ting Chen ,  Chih-Chieh Hung

IPC: H01L27/146 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L27/14634 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L21/4803 ,  H01L27/14627 ,  H01L27/14636 ,  H01L2224/08145 ,  H01L24/08

Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.