公开(公告)号：US09110804B2

公开(公告)日：2015-08-18

申请号：US13681832

申请日：2012-11-20

Applicant: Intel Corporation

Inventor： Eric C. Hannah

IPC: G01T1/00 ,  G06F11/07 ,  G01R31/317 ,  G01R31/3181

CPC classification number: G01T1/247 ,  G01R31/317 ,  G01R31/31816 ,  G06F11/0793

Abstract: Described is a chip comprising: a substrate; a logic unit forming an active circuit on the substrate; and a cosmic ray detector embedded in the substrate, the cosmic ray detector to detect a cosmic ray and to generate a signal indicating detection of the cosmic ray, the signal for reducing error in the logic unit.

Abstract translation: 描述了一种芯片，包括：基板; 在所述基板上形成有源电路的逻辑单元; 宇宙射线检测器，用于检测宇宙射线并产生指示宇宙射线检测的信号，该信号用于减少逻辑单元中的误差。

公开(公告)号：US10777366B2

公开(公告)日：2020-09-15

申请号：US15936427

申请日：2018-03-26

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Zhaohui Chen ,  Wei C. Jin ,  Scott B. Clendenning ,  Eric C. Hannah ,  Tomm V. Aldridge ,  John L. Gustafson

IPC: H01G11/26 ,  H01G11/86 ,  H01G11/58 ,  H01G11/14 ,  H01G11/30

Abstract: Methods of increasing an energy density of an energy storage device involve increasing the capacitance of the energy storage device by depositing a material into a porous structure of the energy storage device using an atomic layer deposition process, by performing a procedure designed to increase a distance to which an electrolyte penetrates within channels of the porous structure, or by placing a dielectric material into the porous structure. Another method involves annealing the energy storage device in order to cause an electrically conductive substance to diffuse to a surface of the structure and form an electrically conductive layer thereon. Another method of increasing energy density involves increasing the breakdown voltage and another method involves forming a pseudocapacitor. A method of increasing an achievable power output of an energy storage device involves depositing an electrically conductive material into the porous structure.

公开(公告)号：US20150187515A1

公开(公告)日：2015-07-02

申请号：US14644632

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Eric C. Hannah ,  Rong Chen ,  John Gustafson

IPC: H01G11/26 ,  H01G11/52 ,  H01G2/02 ,  H01G11/54

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

Abstract translation: 在一个实施例中，电荷存储装置包括通过分离器（130）彼此分离的第一（110）和第二（120）导电结构。 第一和第二导电结构中的至少一个包括包含多个通道（111,121）的多孔结构。 每个通道具有到多孔结构的表面（115,125）的开口（112,122）。 在另一个实施方案中，电荷存储装置包括与至少一些纳米结构物理接触的多个纳米结构（610）和电解质（650）。 具有至少3.9的介电常数的材料（615）可以位于电解质和纳米结构之间。

公开(公告)号：US09989655B2

公开(公告)日：2018-06-05

申请号：US14829485

申请日：2015-08-18

Applicant: INTEL CORPORATION

Inventor： Eric C. Hannah

IPC: G01T1/24 ,  G01R31/317 ,  G06F11/07 ,  G01R31/3181

CPC classification number: G01T1/247 ,  G01R31/317 ,  G01R31/31816 ,  G06F11/0793

Abstract: Described is a chip comprising: a substrate; a logic unit forming an active circuit on the substrate; and a cosmic ray detector embedded in the substrate, the cosmic ray detector to detect a cosmic ray and to generate a signal indicating detection of the cosmic ray, the signal for reducing error in the logic unit.

公开(公告)号：US09368290B2

公开(公告)日：2016-06-14

申请号：US14644632

申请日：2015-03-11

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Eric C. Hannah ,  Rong Chen ,  John Gustafson

IPC: H01G11/26 ,  H01G11/36 ,  H01G11/86 ,  H01G9/048 ,  H01G2/02 ,  H01G11/52 ,  H01G11/54 ,  H01L49/02

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

公开(公告)号：US20160268065A1

公开(公告)日：2016-09-15

申请号：US15163798

申请日：2016-05-25

Applicant: Intel Corporation

Inventor： Donald S. Gardner ,  Eric C. Hannah ,  Rong Chen ,  John L. Gustafson

IPC: H01G11/86 ,  H01G11/24 ,  H01G11/52

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

公开(公告)号：US09406450B2

公开(公告)日：2016-08-02

申请号：US14688937

申请日：2015-04-16

Applicant: Intel Corporation

Inventor： Eric C. Hannah

IPC: H01G9/00 ,  H01G11/84 ,  H01G11/28 ,  H01G11/36 ,  H01G11/68 ,  H01G11/24 ,  H01G11/26 ,  H01G11/30 ,  H01G11/86

CPC classification number: H01G11/84 ,  H01G11/24 ,  H01G11/26 ,  H01G11/28 ,  H01G11/30 ,  H01G11/36 ,  H01G11/68 ,  H01G11/86 ,  Y02E60/13 ,  Y10T29/417

Abstract: In one embodiment, a structure for a energy storage device may include at one polycrystalline substrate. The grain size may be designed to be at least a size at which phonon scattering begins to dominate over grain boundary scattering in the polycrystalline substrate. The structure also includes a porous structure containing multiple channels within the polycrystalline substrate.