公开(公告)号：US20170301309A1

公开(公告)日：2017-10-19

申请号：US15641052

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Fenardi THENUS ,  Peng ZOU ,  Raghu Nandan CHEPURI ,  Henry K. KOERTZEN

IPC: G09G5/00 ,  H02M3/158 ,  H03K7/08 ,  G06F3/041 ,  H03K17/284 ,  H03K7/06 ,  H03K5/14 ,  H02M1/00

CPC classification number: G09G5/006 ,  G06F3/0412 ,  G09G2330/021 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/0009 ,  H02M2001/0032 ,  H02M2003/1586 ,  H03K5/14 ,  H03K7/06 ,  H03K7/08 ,  H03K17/284 ,  Y02B70/16

Abstract: Described is an apparatus that comprises: a programmable delay line (PDL) to receive a pulse-width modulation (PWM) signal as input and to generate a first output; a selection unit operable to provide PWM signal or its inverted version as a second output; and a sequential unit coupled to the PDL, the sequential unit to sample the second output with the first output, the sequential unit to generate a pulse-frequency modulation (PFM) output. Described is also a voltage regulator which comprises: mutually coupled on-die inductors for coupling to a load; a bridge, coupled to the mutually coupled on-die inductors, including a low-side switch and a high-side switch; a PWM controller for controlling the low-side and high-side switches during a first load current; and a PFM controller for controlling the low-side and high-side switches during a second load current, the second load current being smaller than the first load current, the PFM controller comprising: a comparator for comparing output voltage of the load with a reference voltage; and a first PDL coupled to the comparator for determining turn-on duration of the high-side switch.