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公开(公告)号：US10651869B1
公开(公告)日：2020-05-12
申请号：US16364891
申请日：2019-03-26
Applicant: Intel IP Corporation , Intel Corporation
Inventor： Davide Ponton , Michael Kalcher , Alan Paussa , Edwin Thaller , Franz Kuttner , Daniel Gruber
Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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公开(公告)号：US10396815B1
公开(公告)日：2019-08-27
申请号：US16233501
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Franz Kuttner
Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
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公开(公告)号：US09379883B1
公开(公告)日：2016-06-28
申请号：US14571531
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Franz Kuttner , Michael Fulde
CPC classification number: H04L7/0083 , H03M1/068 , H03M1/0863 , H03M1/66 , H03M1/806 , H04L1/22
Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.
Abstract translation: 通信系统接收输入信号并产生转换的输出信号。 控制信号选择性地激活单元阵列中的一个或多个源单元。 所选择的源单元在单元阵列的单元输出端产生第一充电封装和第二充电封装，以产生转换的输出信号。 第一个充电包和第二个充电包在相同的时钟周期内产生。
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公开(公告)号：US10673661B1
公开(公告)日：2020-06-02
申请号：US16367601
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Franz Kuttner , Alexander Belitzer , Florian Mrugalla , Navatouch Deeying
Abstract: Systems, methods, and circuitries enable selected signal components to be isolated in a feedback transmit signal that includes multiple signal components. In one example, a signal component cancellation system for a feedback receiver includes a transmit chain configured to transmit a transmit signal having at least two signal components with offset center frequencies. The system includes measurement circuitry configured to measure a received signal that results from feedback of the transmit signal and cancellation circuitry configured to cancel a selected signal component from the transmit signal to generate a cancellation signal. The system further includes subtraction circuitry configured to combine the cancellation signal with the measured received signal to generate a component signal corresponding to a contribution of the selected signal component to the received signal and provide the component signal to the feedback receiver.
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公开(公告)号：US10601437B1
公开(公告)日：2020-03-24
申请号：US16233450
申请日：2018-12-27
Applicant: Intel Corporation
Inventor： Franz Kuttner
Abstract: CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.
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Patent Agency Ranking
公开(公告)号：US10790849B2
公开(公告)日：2020-09-29
申请号：US16549219
申请日：2019-08-23
Applicant: Intel Corporation
Inventor： Franz Kuttner
Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
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公开(公告)号：US10587354B1
公开(公告)日：2020-03-10
申请号：US16200126
申请日：2018-11-26
Applicant: Intel Corporation
Inventor： Damir Hamidovic , Tobias Buckel , Alexander Klinkan , Franz Kuttner , Jovan Markovic , Peter Preyler
IPC: H04B17/354 , H04L27/26 , H04L27/36 , H04B1/04
Abstract: Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.
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公开(公告)号：US20160173269A1
公开(公告)日：2016-06-16
申请号：US14571531
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Franz Kuttner , Michael Fulde
CPC classification number: H04L7/0083 , H03M1/068 , H03M1/0863 , H03M1/66 , H03M1/806 , H04L1/22
Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.
Abstract translation: 通信系统接收输入信号并产生转换的输出信号。 控制信号选择性地激活单元阵列中的一个或多个源单元。 所选择的源单元在单元阵列的单元输出端产生第一充电封装和第二充电封装，以产生转换的输出信号。 第一个充电包和第二个充电包在相同的时钟周期内产生。
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公开(公告)号：US11750209B2
公开(公告)日：2023-09-05
申请号：US17310860
申请日：2020-02-26
Applicant: Intel Corporation
Inventor： Franz Kuttner
Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50Ω.
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10.发明申请公开(公告)号：US20200212929A1
公开(公告)日：2020-07-02
申请号：US16549219
申请日：2019-08-23
Applicant: Intel Corporation
Inventor： Franz Kuttner
Abstract: High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.
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