公开(公告)号：US20160173269A1

公开(公告)日：2016-06-16

申请号：US14571531

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Franz Kuttner ,  Michael Fulde

IPC: H04L7/00 ,  H04L1/22 ,  H03M1/66

CPC classification number: H04L7/0083 ,  H03M1/068 ,  H03M1/0863 ,  H03M1/66 ,  H03M1/806 ,  H04L1/22

Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

Abstract translation: 通信系统接收输入信号并产生转换的输出信号。 控制信号选择性地激活单元阵列中的一个或多个源单元。 所选择的源单元在单元阵列的单元输出端产生第一充电封装和第二充电封装，以产生转换的输出信号。 第一个充电包和第二个充电包在相同的时钟周期内产生。

公开(公告)号：US12273120B2

公开(公告)日：2025-04-08

申请号：US17358084

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Martin Clara ,  Daniel Gruber ,  Christian Lindholm ,  Michael Fulde ,  Giacomo Cascio

IPC: H03M1/12 ,  H03M1/14 ,  H03M1/36 ,  H03M1/38

Abstract: An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M

公开(公告)号：US09379883B1

公开(公告)日：2016-06-28

申请号：US14571531

申请日：2014-12-16

Applicant: Intel Corporation

Inventor： Franz Kuttner ,  Michael Fulde

IPC: H04L27/00 ,  H04L7/00 ,  H03M1/66 ,  H04L1/22

CPC classification number: H04L7/0083 ,  H03M1/068 ,  H03M1/0863 ,  H03M1/66 ,  H03M1/806 ,  H04L1/22

Abstract: A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

Abstract translation: 通信系统接收输入信号并产生转换的输出信号。 控制信号选择性地激活单元阵列中的一个或多个源单元。 所选择的源单元在单元阵列的单元输出端产生第一充电封装和第二充电封装，以产生转换的输出信号。 第一个充电包和第二个充电包在相同的时钟周期内产生。