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公开(公告)号:US11984246B2
公开(公告)日:2024-05-14
申请号:US17566529
申请日:2021-12-30
Applicant: Intel Corporation
Inventor: Andreas Wolter , Thorsten Meyer , Gerhard Knoblinger
CPC classification number: H01F17/0033 , H01F41/046 , H01L23/5227 , H01L23/645 , H01L24/17 , H01F2017/0086 , H01F2027/2814 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05647 , H01L2224/11 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/16265 , H01L2224/16267 , H01L2224/1703 , H01L2224/171 , H01L2924/19042 , H01L2924/19104 , H01L2924/19107 , H01L2224/0345 , H01L2924/00014 , H01L2224/03462 , H01L2924/00014 , H01L2224/03464 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/1132 , H01L2924/00014 , H01L2224/11334 , H01L2924/00014
Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
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公开(公告)号:US11250981B2
公开(公告)日:2022-02-15
申请号:US16993152
申请日:2020-08-13
Applicant: Intel Corporation
Inventor: Andreas Wolter , Thorsten Meyer , Gerhard Knoblinger
Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
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