公开(公告)号：US10535634B2

公开(公告)日：2020-01-14

申请号：US15106761

申请日：2015-07-22

Applicant: INTEL CORPORATION

Inventor： Vijay K. Nair ,  Chuan Hu ,  Thorsten Meyer

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.

公开(公告)号：US10394280B2

公开(公告)日：2019-08-27

申请号：US15870819

申请日：2018-01-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Dirk Plenkers ,  Hans-Joachim Barth ,  Bernd Waidhas ,  Yen Hsiang Chew ,  Kooi Chi Ooi ,  Howe Yin Loo

IPC: G06F1/16 ,  B29C39/02 ,  B29C39/10 ,  B29C65/48 ,  G02C5/14 ,  G02C11/00 ,  B29L31/34

Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09997444B2

公开(公告)日：2018-06-12

申请号：US15117716

申请日：2014-03-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/50 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US09653439B2

公开(公告)日：2017-05-16

申请号：US14778036

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Sven Albers ,  Andreas Wolter ,  Klaus Reingruber ,  Thorsten Meyer

IPC: H01L25/16 ,  H01L21/50 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L23/31 ,  H01L21/683 ,  H01L23/498 ,  H01L49/02

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

公开(公告)号：US09472515B2

公开(公告)日：2016-10-18

申请号：US14205093

申请日：2014-03-11

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/525

CPC classification number: H01L24/11 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76871 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/821 ,  H01L2224/82105 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/03

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及组装集成电路封装的方法。 在实施例中，该方法可以包括提供具有未图案化钝化层的晶片以防止嵌入晶片中的金属导体的腐蚀。 该方法还可以包括将绝缘材料层压在钝化层上以形成电介质层，并选择性地去除电介质材料以在电介质层中形成空隙。 这些空隙可以露出设置在金属导体上的钝化层的部分。 该方法可以包括去除钝化层的部分以露出金属导体。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160274621A1

公开(公告)日：2016-09-22

申请号：US14778070

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Dirk Plenkers ,  Hans-Joachim Barth ,  Bernd Waidhas ,  Yen Hsiang Chew ,  Kooi Chi Ooi ,  Howe Yin Loo

IPC: G06F1/16 ,  B29C65/48 ,  B29C39/02 ,  B29C39/10 ,  G02C11/00 ,  G02C5/14

CPC classification number: G06F1/163 ,  B29C39/021 ,  B29C39/10 ,  B29C65/4825 ,  B29L2031/3481 ,  G02C5/143 ,  G02C11/10

Abstract: Embodiments of wearable electronic devices, components thereof, and related systems and techniques are disclosed herein. For example, a wearable electronic device may include a wearable support structure having a first surface and a second surface; a first electrode located at the first surface, wherein, when the wearable electronic device is worn by a user on a portion of the user's body, the first electrode is arranged to contact the user's skin in the portion of the user's body; a second electrode located at the second surface, wherein, when the wearable electronic device is worn by a user on the portion of the user's body, the second electrode is arranged to not contact the user's skin in the portion of the user's body; and a resistance switch having first and second input terminals coupled to the first and second electrodes, respectively. Other embodiments may be disclosed and/or claimed.

Abstract translation: 可穿戴式电子设备，其组件以及相关系统和技术的实施例在此公开。 例如，可穿戴电子设备可以包括具有第一表面和第二表面的可穿戴支撑结构; 位于所述第一表面的第一电极，其中当所述可穿戴电子设备被所述用户佩戴在所述用户身体的一部分上时，所述第一电极布置成在所述用户身体的所述部分中接触所述用户的皮肤; 位于所述第二表面的第二电极，其中，当所述可佩戴的电子装置被使用者佩戴在所述使用者身体的所述部分上时，所述第二电极被布置成在所述使用者身体的所述部分中不接触所述使用者的皮肤; 以及电阻开关，其具有分别耦合到第一和第二电极的第一和第二输入端子。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20230023328A1

公开(公告)日：2023-01-26

申请号：US17958298

申请日：2022-09-30

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L21/56 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US10319688B2

公开(公告)日：2019-06-11

申请号：US14361625

申请日：2013-12-09

Applicant: INTEL CORPORATION

Inventor： Andreas Wolter ,  Saravana Maruthamuthu ,  Mikael Knudsen ,  Thorsten Meyer ,  Georg Seidemann ,  Pablo Herrero ,  Pauli Jaervinen

IPC: H01Q1/38 ,  H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01Q1/50 ,  H01Q1/52 ,  H01L23/29

Abstract: An antenna is described on ceramics that may be used for a packaged die. In one example, a package has a die, a ceramic substrate over the die, an antenna attached to the ceramic substrate, and conductive leads electrically connecting the antenna to the die.

公开(公告)号：US20180197840A1

公开(公告)日：2018-07-12

申请号：US15915769

申请日：2018-03-08

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US09991239B2

公开(公告)日：2018-06-05

申请号：US14767902

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Vijay K. Nair ,  Thorsten Meyer

IPC: H01L23/34 ,  H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/162 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16505 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/15331 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.