公开(公告)号：US20240304485A1

公开(公告)日：2024-09-12

申请号：US18609631

申请日：2024-03-19

Applicant: SHARPACK TECHNOLOGY PTE. LTD.

Inventor： Jian Zhang

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/00 ,  H05K13/04 ,  H05K13/08

CPC classification number: H01L21/681 ,  H01L21/67144 ,  H01L21/67259 ,  H01L21/6838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H05K13/0404 ,  H05K13/0409 ,  H05K13/0452 ,  H05K13/046 ,  H05K13/0465 ,  H05K13/0812 ,  H05K13/0882 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/117

Abstract: An arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a donor chuck; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-controlled compression rod so as to bond the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate so as to form an integrated circuit assembly.

公开(公告)号：US12057417B2

公开(公告)日：2024-08-06

申请号：US16739578

申请日：2020-01-10

Applicant: Texas Instruments Incorporated

Inventor： Masamitsu Matsuura ,  Daiki Komatsu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/11013 ,  H01L2224/11334

Abstract: A wafer chip-scale package (WCSP) includes a substrate including a semiconductor surface layer including circuitry configured for at least one function having at least a top metal interconnect layer thereon that includes at least one bond pad coupled to a node in the circuitry. A redistribution layer (RDL) including a bump pad is coupled by a trace to metal filled plugs through a passivation layer to the bond pad. A solder ball is on the bump pad, and a dielectric ring is on the bump pad that has an inner area that is in physical contact with the solder ball.

公开(公告)号：US11990435B2

公开(公告)日：2024-05-21

申请号：US17867287

申请日：2022-07-18

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Sung Sun Park ,  Ji Young Chung ,  Christopher Berry

IPC: G06V40/13 ,  B81C3/00 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31

CPC classification number: H01L24/05 ,  B81C3/00 ,  G06V40/13 ,  G06V40/1329 ,  H01L23/053 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27622 ,  H01L2224/2784 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29299 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81471 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/014 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/1146 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/03452 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/0347 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01074 ,  H01L2224/05671 ,  H01L2924/00014 ,  H01L2224/05666 ,  H01L2924/01028 ,  H01L2224/0361 ,  H01L2924/00014 ,  H01L2224/119 ,  H01L2224/034 ,  H01L2224/1147 ,  H01L2224/034 ,  H01L2224/114 ,  H01L2224/0361 ,  H01L2224/13294 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/014 ,  H01L2224/81203 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/2919 ,  H01L2924/07025 ,  H01L2224/2929 ,  H01L2924/07025 ,  H01L2224/2919 ,  H01L2924/069 ,  H01L2224/2929 ,  H01L2924/069 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/29294 ,  H01L2924/00014 ,  H01L2224/2939 ,  H01L2924/00014 ,  H01L2224/29299 ,  H01L2924/00014 ,  H01L2224/27622 ,  H01L2924/00014 ,  H01L2224/2732 ,  H01L2924/00014 ,  H01L2224/27312 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81424 ,  H01L2924/00014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/8146 ,  H01L2924/00014 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2224/81464 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81466 ,  H01L2924/00014 ,  H01L2224/81471 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/00012 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

公开(公告)号：US11972968B2

公开(公告)日：2024-04-30

申请号：US16873779

申请日：2020-07-02

Applicant: Jian Zhang

Inventor： Jian Zhang

IPC: H01L21/68 ,  H01L21/67 ,  H01L21/683 ,  H01L23/00 ,  H05K13/04 ,  H05K13/08

CPC classification number: H01L21/681 ,  H01L21/67144 ,  H01L21/67259 ,  H01L21/6838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H05K13/0404 ,  H05K13/0409 ,  H05K13/0452 ,  H05K13/046 ,  H05K13/0465 ,  H05K13/0812 ,  H05K13/0882 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/117

Abstract: The present invention features a system and manufacturing arrangement for multiple die chips onto a receiver substrate. The system includes a donor chuck; a receiver chuck configured for supporting the receiver substrate; a pick and place gripper mechanism configured for retrieving a die chip supported on the donor chuck; a gang carrier configured for receiving the die chip from the gripper mechanism; a flipper mechanism configured for delivering the die chip in an inverted orientation relative to the orientation of the die chip when received by the gang carrier; and computer controlled interconnected inspection cameras configured for ensuring accurate alignment of the receiver substrate relative to the die chip in the inverted orientation. The gang carrier has a thermocouple controlled heating element therein to maintain a proper computer controlled temperature therewithin.

公开(公告)号：US11810878B2

公开(公告)日：2023-11-07

申请号：US17115093

申请日：2020-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyung Sun Jang ,  Yeo Hoon Yoon

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02379 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03828 ,  H01L2224/03829 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05547 ,  H01L2224/05559 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/16225 ,  H01L2924/3512

Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

公开(公告)号：US11798860B2

公开(公告)日：2023-10-24

申请号：US17344827

申请日：2021-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Pei-Haw Tsao ,  Chien-Jung Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3185 ,  H01L21/56 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02377 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/3512 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/94 ,  H01L2224/11

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

公开(公告)号：US20230178506A1

公开(公告)日：2023-06-08

申请号：US17917270

申请日：2020-06-05

Applicant: Mitsubishi Electric Corporation

Inventor： Tatsushi MORISADA

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/16 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0603 ,  H01L2224/1131 ,  H01L2224/1369 ,  H01L2224/1624 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13551 ,  H01L2224/13566 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/32245

Abstract: A power semiconductor apparatus includes a conductive circuit pattern, a power semiconductor device, a sealing member, a conductive post, and a conductive post. A first conductive post is connected to the conductive circuit pattern. A second conductive post is connected to the power semiconductor device. The first conductive post includes a metal pin and a conductive bonding member. The conductive post includes a metal pin and a conductive bonding member.

公开(公告)号：US11670609B2

公开(公告)日：2023-06-06

申请号：US17178491

申请日：2021-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chen ,  Ching-Tien Su

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L23/31 ,  H01L21/768 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3142 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/485 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/024 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1146 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/831 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/3512

Abstract: A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

公开(公告)号：US20190221532A1

公开(公告)日：2019-07-18

申请号：US16364104

申请日：2019-03-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Soon Wei WANG ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2223/54406 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/02315 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

公开(公告)号：US20180374809A1

公开(公告)日：2018-12-27

申请号：US16117483

申请日：2018-08-30

Applicant: EoPLex Limited

Inventor： David G. Love ,  Philip Eugene Rogren

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/03003 ,  H01L2224/031 ,  H01L2224/0311 ,  H01L2224/0312 ,  H01L2224/0344 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03505 ,  H01L2224/03845 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/051 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/11428 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0103 ,  H01L2224/03

Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.