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公开(公告)号:US20240304577A1
公开(公告)日:2024-09-12
申请号:US18667720
申请日:2024-05-17
Applicant: Amkor Technology Singapore Holding Pte. Ltd.
Inventor: Sung Sun Park , Ji Young Chung , Christopher Berry
IPC: H01L23/00 , B81C3/00 , G06V40/13 , H01L23/053 , H01L23/31
CPC classification number: H01L24/05 , B81C3/00 , G06V40/13 , G06V40/1329 , H01L23/053 , H01L24/16 , H01L24/32 , H01L24/73 , H01L23/3128 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/27 , H01L24/29 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0345 , H01L2224/03452 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05684 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/13013 , H01L2224/13014 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13294 , H01L2224/133 , H01L2224/16227 , H01L2224/27312 , H01L2224/2732 , H01L2224/27622 , H01L2224/2784 , H01L2224/29006 , H01L2224/29007 , H01L2224/29011 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/29299 , H01L2224/2939 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/8146 , H01L2224/81464 , H01L2224/81466 , H01L2224/81471 , H01L2224/81484 , H01L2224/81815 , H01L2224/8185 , H01L2224/83101 , H01L2224/83102 , H01L2224/83192 , H01L2224/9211 , H01L2224/92125 , H01L2224/92225 , H01L2924/014 , H01L2924/1815 , H01L2924/18161
Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.
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公开(公告)号:US20240282726A1
公开(公告)日:2024-08-22
申请号:US18170581
申请日:2023-02-17
Applicant: NXP USA, INC.
Inventor: Trent Uehling
IPC: H01L23/00
CPC classification number: H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03464 , H01L2224/03912 , H01L2224/0392 , H01L2224/05022 , H01L2224/05027 , H01L2224/05082 , H01L2224/05124 , H01L2224/05155 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/11462 , H01L2224/11849 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/014 , H01L2924/04953
Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.
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公开(公告)号:US20240203917A1
公开(公告)日:2024-06-20
申请号:US18393489
申请日:2023-12-21
Inventor: Rajesh Katkar , Cyprian Emeka Uzoh
CPC classification number: H01L24/05 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/50 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03616 , H01L2224/0362 , H01L2224/0384 , H01L2224/03845 , H01L2224/05013 , H01L2224/05015 , H01L2224/05026 , H01L2224/05076 , H01L2224/05082 , H01L2224/05105 , H01L2224/05109 , H01L2224/05111 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05551 , H01L2224/05554 , H01L2224/05555 , H01L2224/05576 , H01L2224/05578 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/08145 , H01L2224/08146 , H01L2224/80375 , H01L2224/80895
Abstract: A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.
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4.
公开(公告)号:US12015000B2
公开(公告)日:2024-06-18
申请号:US17328563
申请日:2021-05-24
Applicant: Amkor Technology Singapore Holding Pte. Ltd.
Inventor: Bora Baloglu , Curtis Zwenger , Ron Huemoeller
IPC: H01L21/00 , H01L23/00 , H01L25/00 , H01L25/10 , H01L25/065
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/105 , H01L25/50 , H01L25/0657 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/0508 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05572 , H01L2224/05573 , H01L2224/05575 , H01L2224/0558 , H01L2224/05582 , H01L2224/05583 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1147 , H01L2224/13018 , H01L2224/13147 , H01L2224/13155 , H01L2224/1405 , H01L2224/16055 , H01L2224/16145 , H01L2224/16148 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73104 , H01L2224/73204 , H01L2224/80203 , H01L2224/81005 , H01L2224/81141 , H01L2224/81203 , H01L2224/8134 , H01L2224/81385 , H01L2224/81898 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2224/94 , H01L2224/81 , H01L2224/94 , H01L2224/11 , H01L2224/05666 , H01L2924/01028 , H01L2924/013 , H01L2924/00014 , H01L2224/05666 , H01L2924/01074 , H01L2924/013 , H01L2924/00014 , H01L2224/97 , H01L2224/81 , H01L2224/05147 , H01L2924/00014 , H01L2924/013 , H01L2224/05124 , H01L2924/00014 , H01L2924/013 , H01L2224/05139 , H01L2924/00014 , H01L2924/013 , H01L2224/05144 , H01L2924/00014 , H01L2924/013 , H01L2224/05155 , H01L2924/00014 , H01L2924/013 , H01L2224/13147 , H01L2924/00014 , H01L2924/013 , H01L2224/13155 , H01L2924/00014 , H01L2224/05666 , H01L2924/00014 , H01L2924/013 , H01L2224/05671 , H01L2924/00014 , H01L2924/013 , H01L2224/05647 , H01L2924/00014 , H01L2924/013 , H01L2224/05666 , H01L2924/00014 , H01L2924/01028 , H01L2924/013 , H01L2224/05666 , H01L2924/00014 , H01L2924/01074 , H01L2924/013
Abstract: A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.
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5.
公开(公告)号:US11881476B2
公开(公告)日:2024-01-23
申请号:US17664841
申请日:2022-05-24
Applicant: Semtech Corporation
Inventor: Changjun Huang , Jonathan Clark
IPC: H01L25/00 , H01L23/60 , H01L23/495 , H01L27/02 , H01L23/00 , H01L21/768 , H01L25/065 , H01L23/29 , H01L21/56 , H01L23/31 , H01L21/304 , H01L21/78
CPC classification number: H01L25/50 , H01L21/76898 , H01L23/49575 , H01L23/60 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L21/304 , H01L21/561 , H01L21/78 , H01L23/295 , H01L23/3121 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/85 , H01L27/0255 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/0557 , H01L2224/0558 , H01L2224/05548 , H01L2224/05568 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/08146 , H01L2224/08148 , H01L2224/1132 , H01L2224/1134 , H01L2224/1145 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/13025 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16146 , H01L2224/16147 , H01L2224/16227 , H01L2224/16245 , H01L2224/17181 , H01L2224/2929 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4847 , H01L2224/48091 , H01L2224/48145 , H01L2224/48247 , H01L2224/48463 , H01L2224/48465 , H01L2224/73253 , H01L2224/73257 , H01L2224/8082 , H01L2224/80203 , H01L2224/80895 , H01L2224/8182 , H01L2224/81203 , H01L2224/81815 , H01L2224/85203 , H01L2224/85205 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/1033 , H01L2924/10252 , H01L2924/10253 , H01L2924/10272 , H01L2924/10322 , H01L2924/10324 , H01L2924/10329 , H01L2924/10335 , H01L2924/1203 , H01L2924/13091 , H01L2924/141 , H01L2924/143 , H01L2924/1433 , H01L2924/1434 , H01L2924/1461 , H01L2224/13111 , H01L2924/01082 , H01L2224/11901 , H01L2224/11849 , H01L2224/94 , H01L2224/11 , H01L2224/94 , H01L2224/03 , H01L2224/94 , H01L2224/81 , H01L2224/97 , H01L2224/81 , H01L2224/94 , H01L2224/80 , H01L2224/97 , H01L2224/80 , H01L2224/48091 , H01L2924/00014 , H01L2224/48145 , H01L2924/00012 , H01L2224/48465 , H01L2224/48247 , H01L2924/00 , H01L2224/45147 , H01L2924/00014 , H01L2224/45124 , H01L2924/00014 , H01L2224/45144 , H01L2924/00014 , H01L2224/45139 , H01L2924/00014 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.
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公开(公告)号:US11876062B2
公开(公告)日:2024-01-16
申请号:US17624040
申请日:2019-10-08
Applicant: Mitsubishi Electric Corporation
Inventor: Tsuyoshi Osaga
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L2224/03464 , H01L2224/05011 , H01L2224/05083 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2924/13055 , H01L2924/35121
Abstract: The present invention relates to a semiconductor device. The semiconductor device includes: a first main electrode provided on an active region; a second main electrode provided on an opposite side of the semiconductor substrate from the first main electrode; a protection film covering a terminal region; and a non-electrolytic plating layer provided on the first main electrode not covered by the protection film, the first main electrode includes a center electrode in a center part and an outer peripheral electrode provided along the center electrode to be separately from the center electrode, the protection film is provided to extend from the terminal region to an end edge portion of the outer peripheral electrode, the center electrode and the outer peripheral electrode include: a first metal layer; and a second metal layer provided on the first metal layer, and the outer peripheral electrode includes a hole part to reach the first metal layer.
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公开(公告)号:US11862589B2
公开(公告)日:2024-01-02
申请号:US17385586
申请日:2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyung Sun Jang , Yeo Hoon Yoon
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/02379 , H01L2224/03462 , H01L2224/03464 , H01L2224/03828 , H01L2224/03829 , H01L2224/0401 , H01L2224/05541 , H01L2224/05547 , H01L2224/05559 , H01L2224/05573 , H01L2224/05582 , H01L2224/05611 , H01L2224/05639 , H01L2224/11334 , H01L2224/11849 , H01L2224/13006 , H01L2224/13111 , H01L2224/13139 , H01L2224/16225 , H01L2924/3512
Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.
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公开(公告)号:US11824026B2
公开(公告)日:2023-11-21
申请号:US17113480
申请日:2020-12-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Shien Chen , Sheng-Yu Wu , Mirng-Ji Lii , Chita Chuang
IPC: H01L23/00
CPC classification number: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/81 , H01L24/94 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/03614 , H01L2224/03912 , H01L2224/03916 , H01L2224/0401 , H01L2224/05082 , H01L2224/05166 , H01L2224/05187 , H01L2224/05553 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/1132 , H01L2224/1144 , H01L2224/1145 , H01L2224/1147 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/11906 , H01L2224/131 , H01L2224/13007 , H01L2224/13013 , H01L2224/13021 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14131 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/16245 , H01L2224/8183 , H01L2224/81191 , H01L2224/81805 , H01L2224/81815 , H01L2224/81825 , H01L2224/94 , H01L2224/05187 , H01L2924/04953 , H01L2224/05166 , H01L2924/00014 , H01L2224/0345 , H01L2924/00014 , H01L2224/03452 , H01L2924/00014 , H01L2224/131 , H01L2924/014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13124 , H01L2924/00014 , H01L2224/13144 , H01L2924/00014 , H01L2224/13155 , H01L2924/00014 , H01L2224/13139 , H01L2924/00014 , H01L2224/13164 , H01L2924/00014 , H01L2224/13111 , H01L2924/00014 , H01L2224/13109 , H01L2924/00014 , H01L2224/1145 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/1132 , H01L2924/00014 , H01L2224/11334 , H01L2924/00014 , H01L2224/1144 , H01L2924/00014 , H01L2224/11464 , H01L2924/00014 , H01L2224/03462 , H01L2924/00014 , H01L2224/1147 , H01L2924/00012 , H01L2224/94 , H01L2224/03 , H01L2224/94 , H01L2224/11 , H01L2224/05624 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/05684 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/03464 , H01L2924/00014 , H01L2224/81815 , H01L2924/00014 , H01L2224/81805 , H01L2924/00014 , H01L2224/81825 , H01L2924/00014 , H01L2224/8183 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014
Abstract: Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first patterned passivation layer having a first opening exposing a conductive feature of the workpiece. A seed layer is formed over the first patterned passivation layer and in the first opening. A patterned mask layer is formed over the seed layer, the patterned mask layer having a second opening exposing the seed layer, the second opening overlapping with the first opening. A connector is formed in the second opening. The patterned mask layer is partially removed, an unremoved portion of the patterned mask layer remaining in the first opening. The seed layer is patterned using the unremoved portion of the patterned mask layer as a mask.
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公开(公告)号:US11791286B2
公开(公告)日:2023-10-17
申请号:US17405487
申请日:2021-08-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Youn-ji Min , Seok-hyun Lee
IPC: H01L23/00
CPC classification number: H01L23/562 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/11 , H01L2224/02125 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/05022 , H01L2224/05024 , H01L2224/05027 , H01L2224/05554 , H01L2224/05555 , H01L2224/05556 , H01L2224/05557 , H01L2224/05559 , H01L2224/05572 , H01L2224/1132 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/13021 , H01L2224/13023 , H01L2924/3512 , H01L2924/35121 , H01L2224/05556 , H01L2924/00012 , H01L2224/03462 , H01L2924/00014 , H01L2224/03464 , H01L2924/00014 , H01L2224/1132 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/11464 , H01L2924/00014 , H01L2224/11849 , H01L2924/00014
Abstract: Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.
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公开(公告)号:US11791243B2
公开(公告)日:2023-10-17
申请号:US17815515
申请日:2022-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Chia Hu , Sen-Bor Jan , Hsien-Wei Chen , Ming-Fa Chen
IPC: H01L23/48 , H01L23/528 , H01L21/768 , H01L21/66 , H01L23/00
CPC classification number: H01L23/481 , H01L21/76805 , H01L22/32 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/09 , H01L24/80 , H01L24/08 , H01L2224/03 , H01L2224/03462 , H01L2224/03464 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05647 , H01L2224/0603 , H01L2224/08146 , H01L2224/08235 , H01L2224/80447 , H01L2225/06513 , H01L2225/06524 , H01L2225/06596 , H01L2924/14 , H01L2224/05147 , H01L2924/013 , H01L2924/00014 , H01L2224/05124 , H01L2924/013 , H01L2924/00014 , H01L2224/05647 , H01L2924/013 , H01L2924/00014 , H01L2224/05166 , H01L2924/00014 , H01L2224/05186 , H01L2924/04941 , H01L2924/00014 , H01L2224/05181 , H01L2924/00014 , H01L2224/05186 , H01L2924/04953 , H01L2924/00014 , H01L2224/80447 , H01L2924/013 , H01L2924/00014 , H01L2224/05147 , H01L2924/00014
Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
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