公开(公告)号：US09812189B2

公开(公告)日：2017-11-07

申请号：US14731319

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Wei-Hsiang Ma ,  Gunjan H. Pandya

IPC: G11C11/00 ,  G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

公开(公告)号：US09208853B2

公开(公告)日：2015-12-08

申请号：US13842086

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

IPC: G11C11/40 ,  G11C11/412 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract translation: 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。

公开(公告)号：US09607687B2

公开(公告)日：2017-03-28

申请号：US14948196

申请日：2015-11-20

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

IPC: G11C11/40 ,  G11C11/419 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

公开(公告)号：US20160358643A1

公开(公告)日：2016-12-08

申请号：US14731319

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Pramrod Kolar ,  Wei-Hsiang Ma ,  Gunjan H. Pandya

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418

Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.

Abstract translation: 提供了一种装置，包括：存储器阵列; 用于检测存储器阵列的行的第一和第二字线（WL）是否处于活动状态的第一逻辑; 以及第二逻辑，用于停用所述第一和第二WL中的一个，使得所述第一和第二WL中的一个对于所述行是活动的。

公开(公告)号：US20160078926A1

公开(公告)日：2016-03-17

申请号：US14948196

申请日：2015-11-20

Applicant: Intel Corporation

Inventor： Pramod Kolar ,  Gunjan H. Pandya ,  Uddalak Bhattacharya ,  Zheng Guo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit.

Abstract translation: 在一个实施例中，用于存储数据的存储单元电路包括一对交叉耦合的反相器，用于存储存储单元电路的状态。 接入设备提供对一对交叉耦合逆变器的访问。 存储单元电路还包括耦合到该对交叉耦合的反相器的一组电活性p型金属氧化物半导体（PMOS）器件。 与一对交叉耦合的反相器的一部分（例如，PMOS器件）组合的一组非活性PMOS器件使得能够存储单元电路的连续p型扩散层。