公开(公告)号：US20240013851A1

公开(公告)日：2024-01-11

申请号：US18372605

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Hang CHEN ,  Shen ZHOU ,  Kuljit S. BAINS ,  Mohan J. KUMAR ,  Antonio J. HASBUN MARIN

IPC: G11C29/52 ,  G11C29/00 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C29/883 ,  G11C11/40618

Abstract: A system provides DO-level sparing to spare a fault of a data signal (DQ) line of a memory bus. The data bus has multiple data dynamic random access memory (DRAM) devices and at least one error correction code (ECC) DRAM device coupled to it. An error manager can be in the memory controller or in a platform error controller. The error manager to detect a DQ failure and dynamically switches ECC mode on the fly. The error manager can map out data bits of the DQ and remap ECC bits of the at least one ECC DRAM device to the mapped out data bits of the DQ.