公开(公告)号：US20220350715A1

公开(公告)日：2022-11-03

申请号：US17865095

申请日：2022-07-14

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Tai HUANG ,  Kuljit S. BAINS

IPC: G06F11/20

Abstract: A system can respond to detection or prediction of an uncorrectable error (UE) in memory based on fault-aware analysis. The fault-aware analysis enables the system to generate a determination of a specific hardware element of the memory that is faulty. In response to detection of an error, the system can correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration. Based on a determination of the specific component that likely caused the UE, the system can identify a region of memory associated with the detected UE and mirror the faulty region to a reserved memory space of the memory device for access to data of the faulty region.

公开(公告)号：US20230083193A1

公开(公告)日：2023-03-16

申请号：US17348435

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Xiaoming DU ,  Cong LI ,  Kuljit S. BAINS ,  Rajat AGARWAL ,  Murugasamy K. NACHIMUTHU ,  Maciej LAWNICZAK ,  Chao Yan TANG ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

公开(公告)号：US20210279122A1

公开(公告)日：2021-09-09

申请号：US17317745

申请日：2021-05-11

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Xiaoming DU ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: Methods and apparatus for lifetime telemetry on memory error statistics to improve memory failure analysis and prevention. Memory error information corresponding to detected correctable errors and uncorrectable memory errors are monitored, with the memory error information identifying an associated DRAM device in an associated DIMM. Corresponding micro-level error bits information from the memory error information is decoded and Micro-level Error Statistic Indicators (MESIs) are generated. Information associated with the MESIs from DRAM devices on the DIMMs are periodically written to persistent storage on those DIMMs. The MESIs for a given DIMM are updated over the lifetime of the DIMM.

公开(公告)号：US20180077537A1

公开(公告)日：2018-03-15

申请号：US15564708

申请日：2015-06-03

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Zhijie SHENG ,  Thanunathan RANGARAJAN ,  Junjie HUANG

IPC: H04W4/04 ,  H04W4/00 ,  G06F21/44 ,  G06F21/57 ,  G06F9/455

CPC classification number: H04W4/043 ,  G06F9/45533 ,  G06F21/44 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F2221/2111 ,  H04W4/33 ,  H04W4/50 ,  H04W4/80

Abstract: Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.

公开(公告)号：US20240241778A1

公开(公告)日：2024-07-18

申请号：US18562237

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Kuljit S. BAINS ,  Ugonna ECHERUO ,  Reza E. DAFTARI ,  Theodros YIGZAW ,  Mariusz ORIOL

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/079 ,  G06F11/0793

Abstract: A system (204) can respond to detection of an uncorrectable error (UE) (254) in memory (246) based on fault-aware analysis. The fault-aware analysis enables the system (204) to generate a determination of a specific hardware element of the memory (246) that caused the detected UE (254). In response to detection of a UE (254), the system (204) can correlate a hardware configuration (256) of the memory (246) device with historical data indicating memory (246) faults for hardware elements of the hardware configuration (256). Based on a determination of the specific component that likely caused the UE (254), the system (204) can issue a corrective action for the specific hardware element based on the determination.

公开(公告)号：US20240054039A1

公开(公告)日：2024-02-15

申请号：US18258298

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Vasudevan SRINIVASAN ,  Knut GRIMSRUD ,  Johan VAN DE GROENENDAAL ,  Mariusz ORIOL ,  Nishi AHUJA ,  Shen ZHOU ,  Samantha ALT ,  Katalin BARTFAI-WALCOTT ,  Arkadiusz BERENT

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/076

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature configuration pay-as-you-go licensing are disclosed. A disclosed silicon semiconductor device includes a first counter that increments a first count when a timer expires and, responsive to expiration of the timer, a feature configuration sampler to sample a state of a configuration of a feature of the silicon semiconductor device. In addition, the silicon semiconductor device includes a second counter that increments a second count when the sampled state of the configuration of the feature indicates the feature is active. A feature up-time tracker is also included outputs a value representative of an amount of time the configuration has been active, where the amount of time is based on the first count and the second count.

公开(公告)号：US20240013851A1

公开(公告)日：2024-01-11

申请号：US18372605

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Hang CHEN ,  Shen ZHOU ,  Kuljit S. BAINS ,  Mohan J. KUMAR ,  Antonio J. HASBUN MARIN

IPC: G11C29/52 ,  G11C29/00 ,  G11C11/406

CPC classification number: G11C29/52 ,  G11C29/883 ,  G11C11/40618

Abstract: A system provides DO-level sparing to spare a fault of a data signal (DQ) line of a memory bus. The data bus has multiple data dynamic random access memory (DRAM) devices and at least one error correction code (ECC) DRAM device coupled to it. An error manager can be in the memory controller or in a platform error controller. The error manager to detect a DQ failure and dynamically switches ECC mode on the fly. The error manager can map out data bits of the DQ and remap ECC bits of the at least one ECC DRAM device to the mapped out data bits of the DQ.