公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

公开(公告)号：US20230197538A1

公开(公告)日：2023-06-22

申请号：US17555654

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mohammad Enamul KABIR ,  Conor P. PULS ,  Tofizur RAHMAN ,  Keith ZAWADZKI ,  Hannes GREVE

IPC: H01L23/04 ,  H01L27/088 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/04 ,  H01L27/088 ,  H01L23/564 ,  H01L23/5384

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.