公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

公开(公告)号：US20240332301A1

公开(公告)日：2024-10-03

申请号：US18129871

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Caleb BARRETT ,  Prashant WADHWA ,  Chun-Kuo HUANG ,  Conor P. PULS ,  Daniel James HARRIS ,  Giorgio MARIOTTINI ,  Patrick MORROW

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.