公开(公告)号：US20250029892A1

公开(公告)日：2025-01-23

申请号：US18223413

申请日：2023-07-18

Applicant: Intel Corporation

Inventor： Conor P. PULS ,  Giorgio MARIOTTINI ,  Brenden ARRUDA ,  Shawna M. LIFF ,  Lei JIANG ,  Samson ODUNUGA ,  Gerardo MONTANO ,  Hannes GREVE ,  Apratim DHAR ,  Aaron M. WHITE

IPC: H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

公开(公告)号：US20240363628A1

公开(公告)日：2024-10-31

申请号：US18767458

申请日：2024-07-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20220093589A1

公开(公告)日：2022-03-24

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.