公开(公告)号：US20250098249A1

公开(公告)日：2025-03-20

申请号：US18467859

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Avijit Barik ,  Tao Chu ,  Minwoo Jang ,  Tofizur RAHMAN ,  Conor P. Puls ,  Ariana E. Bondoc ,  Diane Lancaster ,  Chi-Hing Choi ,  Derek Keefer

IPC: H01L29/45 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

公开(公告)号：US20200313075A1

公开(公告)日：2020-10-01

申请号：US16367129

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Angeline SMITH ,  Tanay GOSAVI ,  Sasikanth MANIPATRUNI ,  Kaan OGUZ ,  Kevin O'Brien ,  Benjamin BUFORD ,  Tofizur RAHMAN ,  Rohan PATIL ,  Nafees KABIR ,  Michael CHRISTENSON ,  Ian YOUNG ,  Hui Jae YOO ,  Christopher WIEGAND

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32

Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.

公开(公告)号：US20250105095A1

公开(公告)日：2025-03-27

申请号：US18471356

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Bozidar Marinkovic ,  Benjamin Kriegel ,  Payam Amin ,  Dolly Natalia Ruiz Amador ,  Thomas Jacroux ,  Makram Abd El Qader ,  Tofizur RAHMAN ,  Xiandong Yang ,  Conor P. Puls

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/528

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

公开(公告)号：US20230317563A1

公开(公告)日：2023-10-05

申请号：US17711008

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Payam AMIN ,  Tofizur RAHMAN ,  Bozidar MARINKOVIC ,  Santhosh Kumar KODURI ,  Tugba KOKER AYKOL ,  Jayeeta SEN ,  David BENNETT ,  Conor P. PULS ,  Clay MORTENSEN ,  Leslie L. CHAN ,  Hoang DOAN ,  Dolly Natalia RUIZ AMADOR

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696 ,  H01L23/5283 ,  H01L23/53257 ,  H01L21/76898

Abstract: Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.

公开(公告)号：US20250140748A1

公开(公告)日：2025-05-01

申请号：US18498519

申请日：2023-10-31

Applicant: Intel Corporation

Inventor： Payam Amin ,  Mandip Sibakoti ,  Bozidar Marinkovic ,  Tofizur RAHMAN ,  Conor P. Puls

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.

公开(公告)号：US20250132245A1

公开(公告)日：2025-04-24

申请号：US18491111

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Conor P. Puls ,  Payam Amin ,  Santhosh Koduri ,  Clay Mortensen ,  Bozidar Marinkovic ,  Shivani Falgun Patel ,  Richard Bonsu ,  Jaladhi Mehta ,  Dincer Unluer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.

公开(公告)号：US20230197538A1

公开(公告)日：2023-06-22

申请号：US17555654

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Mohammad Enamul KABIR ,  Conor P. PULS ,  Tofizur RAHMAN ,  Keith ZAWADZKI ,  Hannes GREVE

IPC: H01L23/04 ,  H01L27/088 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/04 ,  H01L27/088 ,  H01L23/564 ,  H01L23/5384

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.

公开(公告)号：US20180322994A1

公开(公告)日：2018-11-08

申请号：US15773339

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Daniel B. BERGSTROM

IPC: H01F10/32 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F41/32

CPC classification number: H01F10/3254 ,  G11C11/161 ,  H01F10/3272 ,  H01F41/32 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the disclosure are directed to a magnetic tunneling junction (MTJ) that includes a diffusion barrier. The diffusion barrier can be disposed between two ferromagnetic layers of the MTJ. More specifically, the diffusion barrier can be disposed between a first ferromagnetic layer, which is adjacent to a natural antiferromagnetic layer, and a second ferromagnetic layer; the first and second ferromagnetic layers and the diffusion barrier being part of a synthetic antiferromagnet. The diffusion barrier can be made of a refractory metal, such as tantalum. The diffusion barrier acts as a barrier for manganese diffusion from the natural antiferromagnetic layer into the synthetic antiferromagnet and other higher layers of the MTJ.